AM79C976 Advanced Micro Devices, AM79C976 Datasheet - Page 104

• Manufacturer Part Number: AM79C976
• Description: PCnet-PRO 10/100 Mbps PCI Ethernet Controller
• Manufacturer: Advanced Micro Devices

Instruction Register and Decoding Logic
After the TAP FSM is reset, the IDCODE instruction is
always invoked. The decoding logic gives signals to con-
trol the data flow in the Data registers according to the
current instruction.
Each Boundary Scan Register (BSR) cell has two
stages. A flip-flop and a latch are used for the Serial
Shift Stage and the Parallel Output Stage, respectively.
There are four possible operation modes in the BSR
cell shown in Table 18.
Other data registers are the following:
1. Bypass Register (1 bit)
2. Device ID register (32 bits) (Table 19).
104
Instruction
SAMPLE
EXTEST
IDCODE
SETBYP
BYPASS
TRIBYP
Name
Table 17. IEEE 1149.1 Supported Instruction
Table 18. BSR Mode Of Operation
Instruc-
Code
0000
0001
0010
0011
0100
1111
tion
Summary
External
Test
ID Code
Inspection
Sample
Boundary
Force Float
Control
Boundary To
1/0
Bypass
Scan
Description
Normal
Normal
Normal
Normal
Mode
Test
Test
P R E L I M I N A R Y
Selected
Register
ID REG
Bypass
Bypass
Bypass
Data
BSR
BSR
Am79C976
.
Note: The content of the Device ID register is the
same as the content of CSR88.
Reset
There are five different types of RESET operations that
may be p er fo r med on th e A m79 C976 dev ic e,
H_RESET, EE_RESET, S_RESET, STOP, and POR.
The following is a description of each type of RESET
operation.
Hardware Reset (H_RESET) is an Am79C976 reset
operation that has been created by the proper asser-
tion of the RST pin of the Am79C976 device while the
PG pin is HIGH. When the minimum pulse width timing
as specified in the RST pin description has been satis-
fied, then an internal reset operation will be performed.
H_RESET will program most of the CSR and BCR reg-
isters to their default value. Note that there are several
CSR and BCR registers that are undefined after
H_RESET. See the sections on the individual registers
for details.
H_RESET will clear most of the registers in the PCI
configuration space. H_RESET will reset the internal
state machines. Following the end of the H_RESET op-
eration, the Am79C976 controller will attempt to read
the EEPROM device through the EEPROM interface.
H_RESET will clear DWIO (BCR18, bit 7) and the
Am79C976 controller will be in 16-bit I/O mode after
the reset operation. A DWord write operation to the
RDP (I/O offset 10h) must be performed to set the
device into 32-bit I/O mode.
Prior to starting a read of the serial EEPROM, the
Am79C976 controller resets all the registers that can
be programmed from the EEPROM. This provides a
consistent starting point for register programming.
EE_RESET is also generated following EEPROM read
if the EEPROM CRC check fails.
Bits 31-28
Bits 27-12
Bits 11-1
Bit 0
Table 19. Device ID Register
Version
Part Number:
(2628h)
Manufacturer ID. The 11 bit manufacturer ID
code for AMD is 00000000001 in accordance
with JEDEC publication 106-A.
Always a logic 1
0010 0110 0010 1000b
8/01/00