AM79C976 Advanced Micro Devices, AM79C976 Datasheet - Page 224

• Manufacturer Part Number: AM79C976
• Description: PCnet-PRO 10/100 Mbps PCI Ethernet Controller
• Manufacturer: Advanced Micro Devices

7
6-0
Note: This register is used to control and indirectly ac-
cess the Pattern Match RAM (PMR). When BCR45 is
written and the PMAT_MODE bit (bit 7) is 1, Pattern
Match logic is enabled. No bus accesses into PMR are
possible, and BCR46, BCR47, and all other bits in
BCR45 are ignored. When PMAT_MODE is set, a read
of BCR45, BCR46, or BCR47 returns all undefined bits
except for PMAT_MODE.
When BCR45 is written and the PMAT_MODE bit is 0,
the Pattern Match logic is disabled and accesses to the
PMR are possible. Bits 6-0 of BCR45 specify the ad-
dress of the PMR word to be accessed. Following the
write to BCR45, the PMR word may be read by reading
BCR45, BCR46 and BCR47 in any order. To write to
PMR word, the write to BCR45 must be followed by a
write to BCR46 and a write to BCR47 in that order to
complete the operation. The RAM will not actually be
written until the write to BCR47 is complete. The write
to BCR47 causes all 5 bytes (four bytes of BCR46-47
and the upper byte of the BCR45) to be written to what-
ever PMR word is addressed by bits 6:0 of BCR45.
Bit
31-16
224
PMAT_MODE
PMR_ADDR Pattern Match Ram Address.
Name
RES
H_RESET, and is unaffected by
S_RESET and the STOP bit.
Pattern Match Mode. Writing a 1
to this bit will enable Pattern
Match Mode and should only be
done after the Pattern Match
RAM has been programmed.
PMAT_MODE is reset to 0 when
power is initially applied to the de-
vice,
S_RESET and the STOP bit.
These bits are the Pattern Match
Ram address to be written to or
read from.
PMR_ADDR is reset to 0 when
power is first applied to the de-
vice (after power-on reset), and is
unaffected
S_RESET and the STOP bit.
zeros and read as undefined.
Read
Read
Reserved locations. Written as
Description
and
and
and
is
write
write
by
unaffected
P R E L I M I N A R Y
accessible.
accessible.
H_RESET,
Am79C976
by
15-8
7-0
Note: This register is used to control and indirectly ac-
cess the Pattern Match RAM (PMR). When BCR45 is
written and the PMAT_MODE bit (bit 7) is 1, Pattern
Match logic is enabled. No bus accesses into PMR are
possible, and BCR46, BCR47, and all other bits in
BCR45 are ignored. When PMAT_MODE is set, a read
of BCR45, BCR46, or BCR47 returns all undefined bits
except for PMAT_MODE.
When BCR45 is written and the PMAT_MODE bit is 0,
the Pattern Match logic is disabled and accesses to the
PMR are possible. Bits 6-0 of BCR45 specify the ad-
dress of the PMR word to be accessed. Following the
write to BCR45, the PMR word may be read by reading
BCR45, BCR46 and BCR47 in any order. To write to
PMR word, the write to BCR45 must be followed by a
write to BCR46 and a write to BCR47 in that order to
complete the operation. The RAM will not actually be
written until the write to BCR47 is complete. The write
to BCR47 causes all 5 bytes (four bytes of BCR46-47
and the upper byte of the BCR45) to be written to what-
ever PMR word is addressed by bits 6:0 of BCR45.
When PMAT_MODE is 0, the contents of the word ad-
dressed by bits 6:0 of BCR45 can be read by reading
BCR45-47 in any order.
Bit
31-16 RES
15-8
PMR_B2
PMR_B1
Name
PMR_B4
byte is written into or read from
Byte 2 of the Pattern Match RAM.
PMR_B2
H_RESET, and is unaffected by
S_RESET and the STOP bit.
byte is written into or read from
Byte 1 of Pattern Match RAM.
PMR_B1
H_RESET, and is unaffected by
S_RESET and the STOP bit.
Reserved locations. Written as
zeros and read as undefined.
byte is written into or read from
Byte 4 of Pattern Match RAM.
PMR_B4
H_RESET, and is unaffected by
S_RESET and the STOP bit.
Pattern Match RAM Byte 2. This
Read
Pattern Match RAM Byte 1. This
Read
Description
Pattern Match RAM Byte 4. This
Read
and
and
and
is
is
is
write
write
write
undefined
undefined
undefined
accessible.
accessible.
accessible.
8/01/00
after
after
after