AM79C976 Advanced Micro Devices, AM79C976 Datasheet - Page 140

• Manufacturer Part Number: AM79C976
• Description: PCnet-PRO 10/100 Mbps PCI Ethernet Controller
• Manufacturer: Advanced Micro Devices

Offset 06Ch
This register contains several miscellaneous control
bits. Each byte of this register controls a single func-
tion. It is not necessary to do a read-modify-write oper-
ation to change a function’s settings if only a single byte
of the register is written.
140
31-26
25-24
23:18
11-8
Bit
7-5
3-0
Bit
4
BURST_ALIGN
BURST_LIMIT
SLOTMOD
ROMTMG
Name
Name
RES
RES
RES
Reserved locations. Written as zeros and read as undefined.
Slot Time Modulation. This field determines the value of the slot time parameter used for the MAC
half-duplex backoff algorithm.
If SLOTMOD is set to anything other than the default value of 0, the controller will not conform to
IEEE Std 802.3.
Reserved locations. Written as zeros and read as undefined.
Expansion ROM Timing. The value of ROMTMG is used to tune the timing for all accesses to the
external Flash/EPROM.
ROMTMG defines the amount of time that a valid address is driven on the ERA[19:0] pins.
The register value specifies delay in number of ROMCLK cycles, where ROMCLK is an internal
clock signal that runs at one fourth the speed of ERCLK.
Note: Programming ROMTMG with a value of 0 is not permitted.
To ensure adequate expansion ROM setup time, ROMTMG should be set to 1 plus tACC /
(ROMCLK period), where tACC is the access time of the expansion ROM device (Flash or
EPROM). (The extra ROMCLK cycle is added to account for the ERA[19:0] output delay from
ROMCLK plus the ERD[7:0] setup time to ROMCLK.)
ROMTMG is set to the default value of 1001b by H_RESET. It is also set to its default value before
the EEPROM read process starts or when the EEPROM read process fails. The default value
allows using an Expansion ROM with an access time of 350 ns if ERCLK is running at 90 MHz.
This field is an alias of BCR18, bits 15:12.
Reserved locations. Written as zeros and read as undefined.
PCI Bus Burst Align. When this bit is set, if a burst transfer starts in the middle of a cache line, the
transfer will stop at the first cache line boundary.
PCI Bus Burst Limit. This 4-bit field limits the maximum length of a burst transfer. If the contents
of this register are 0, the burst length is limited by the amount of data available or by the amount
of FIFO space available. If the contents of this field are not zero, a burst transfer will end when the
transfer has crossed the number of cache line boundaries equal to the contents of this field.
Table 47.
P R E L I M I N A R Y
CTRL1: Control1 Register
Am79C976
Value
00
01
10
11
All bits in this register are set to their default values by
H_RESET. All bits are also set to their default values
before EEPROM data are loaded or after an EEPROM
read failure.
The default value for all bits except for bits 17:16
(XMTSP) and bits 1:0 (RCVFW) is 0. The default value
for the XMTSP field is 01b (64 bytes). The default value
for the RCVFW field is also 01b.
Description
Description
Slot Time (bits)
512 (standard)
Reserved
1024
256
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