AM79C976 Advanced Micro Devices, AM79C976 Datasheet - Page 118

• Manufacturer Part Number: AM79C976
• Description: PCnet-PRO 10/100 Mbps PCI Ethernet Controller
• Manufacturer: Advanced Micro Devices

Bit
31-24
23-11
10-1
0
118
Name
ROMBASE Expansion ROM base address
ROMSIZE
ZEROS
ROMEN
most significant 8 bits. These bits
are written by the host to specify
the location of the Expansion
ROM in PCI memory space.
ROMBASE must be written with a
valid
Am79C976 Expansion ROM ac-
cess
ROMEN (PCI Expansion ROM
Base Address register, bit 0) and
MEMEN (PCI Command register,
bit 1).
When the Am79C976 controller
is enabled for Expansion ROM
access (ROMEN and MEMEN
are set to 1), it monitors the PCI
bus for a valid memory com-
mand. If the value on AD[31:2]
during the address phase of the
cycle falls in the address space
specified by the contents of this
register, the Am79C976 control-
ler will drive DEVSEL indicating it
will respond to the access.
ROMBASE is read and written by
the host. ROMBASE is cleared
by H_RESET and is not affected
by S_RESET or by setting the
STOP bit.
bits [23:11]. Those bits in this
field that are enabled by the cor-
responding bits in the ROM Con-
figuration Register (ROM_CFG)
are written by the host CPU to
specify the location of the Expan-
sion ROM in PCI memory space.
Those bits in this field that are not
enabled by the corresponding
bits in ROM_CFG are fixed at 0.
has no effect.
by the host to enable access to
the
Am79C976 controller will only re-
spond to accesses to the Expan-
sion ROM when both ROMEN
and MEMEN (PCI Command reg-
ister, bit 1) are set to 1. This bit
can be set to 1 only when bit 0 of
Expansion ROM base address
Read as zeros; write operation
Expansion ROM Enable. Written
Description
Expansion
is
address
enabled
before
ROM.
by
P R E L I M I N A R Y
setting
The
the
Am79C976
Offset 34h
Bit
7-0
Offset 3Ch
The PCI Interrupt Line register is an 8-bit register that
is used to communicate the routing of the interrupt.
This register is written by the POST software as it ini-
tializes the Am79C976 controller in the system. The
register is read by the network driver to determine the
interrupt channel which the POST software has as-
signed to the Am79C976 controller. The PCI Interrupt
Line register is not modified by the Am79C976 control-
ler. It has no effect on the operation of the device.
The PCI Interrupt Line register is read and written by
the host. It is cleared by H_RESET and is not affected
by S_RESET or by setting the STOP bit.
Offset 3Dh
This PCI Interrupt Pin register is an 8-bit register that
indicates the interrupt pin that the Am79C976 controller
is using. The value for the Am79C976 Interrupt Pin reg-
ister is 01h, which corresponds to INTA.
The PCI Interrupt Pin register is read only.
Offset 3Eh
The PCI MIN_GNT register is an 8-bit register that
specifies the minimum length of a burst period that the
Am79C976 device needs to keep up with the network
activity. The length of the burst period is calculated as-
suming a clock rate of 33 MHz. The register value spec-
ifies the time in units of 1/4 µs. The PCI MIN_GNT
register is an alias of the Minimum Grant Shadow Reg-
Name
CAP_PTR
ROMEN is read and written by
the host. ROMEN is cleared by
H_RESET and is not effected by
S_RESET or by setting the STOP
bit.
ROM_CFG is set to 1. When bit 0
of ROM_CFG is cleared to 0,
ROMEN is fixed a 0, and the Ex-
pansion ROM cannot be mapped
into PCI memory space.
Register is a read-only 8-bit reg-
ister that points to a linked list of
capabilities implemented on this
device. This register has the val-
ue 44h.
read only.
Description
The PCI Capabilities pointer
The PCI Capabilities register is
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