AM79C976 Advanced Micro Devices, AM79C976 Datasheet - Page 65

• Manufacturer Part Number: AM79C976
• Description: PCnet-PRO 10/100 Mbps PCI Ethernet Controller
• Manufacturer: Advanced Micro Devices

By default, whenever the DMA controller finishes copy-
ing a transmit frame from system memory, it sets the
TINT bit of CSR0 to indicate that the buffers are no
longer needed. This causes an interrupt signal if the
IENA bit of CSR0 has been set and the TINTM bit of
CSR3 is cleared.
The Am79C976 controller provides two modes to re-
duce the number of transmit interrupts. If the contents
of the Delayed Interrupt Register is not zero, the inter-
rupt to the CPU will be postponed until a programmable
number of interrupt events have occurred or a program-
mable amount of time has elapsed since the first inter-
rupt event occurred. Another mode, which is enabled
by setting LTINTEN (CSR5, bit 14) to 1, allows sup-
pression of interrupts for transmissions of all but the
last frame in a sequence.
If the Am79C976 controller does not own both the cur-
rent and the next receive descr iptor, then the
Am79C976 controller will continue to poll according to
the polling sequence described in the Transmit Polling
section. If the receive descriptor ring length is one, then
there is no next descriptor to be polled.
If a poll operation has revealed that the current and the
next receive descriptors belong to the Am79C976 con-
troller, then additional poll accesses are not necessary.
Future poll operations will not include receive descrip-
tor accesses as long as the Am79C976 controller re-
tains ownership of the current and the next receive
descriptors.
When receive activity is present on the channel, the
Am79C976 controller waits until the number of bytes
specified in the RCV_PROTECT register (default 64)
have been received. If the frame is accepted based on
all active addressing schemes at that time, the DMU is
notified that a frame has been received.
As receive buffers become available in system mem-
ory, the DMA controller will copy frame data from the re-
ceive FIFO into system memory. The Am79C976
controller will set the STP bit in the first descriptor of a
frame. If the frame length exceeds the length of the cur-
rent buffer, the Am79C976 controller will pass owner-
ship back to the system by writing 0s to the OWN and
ENP bits of the descriptor when the first buffer is full.
This activity continues until the Am79C976 controller
recognizes the completion of the frame (the last byte of
this receive message has been removed from the
FIFO). The Am79C976 controller will subsequently up-
date the current receive descriptor with the frame sta-
tus (message byte count, VLAN info, frame tag, error
flags, etc.) and will set the ENP bit to 1. The Am79C976
controller will then advance the internal ring pointer to
make the next receive descriptor the new current re-
ceive descriptor.
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P R E L I M I N A R Y
Am79C976
When the Am79C976 controller has receive data in the
FIFO ready to write to system memory, either at the be-
ginning of a new frame or in the middle of a frame that
does not fit in the previous buffer, and it does not own
the current receive descriptor, it will immediately poll it.
If the OWN bit is still zero, polling of this descriptor will
continue at a rate determined by the contents of the
CHPOLLINT register (CSR49). Polling will occur imme-
diately if the RDMD bit is set.
If the driver does not provide the Am79C976 controller
with a descriptor in a timely fashion, the receive FIFO
will eventually overflow. Subsequent frames will be dis-
carded and the RcvMissPkts MIB counter will be incre-
mented. Normal receive operation will resume when a
descriptor is provided to the Am79C976 controller and
sufficient data has been DMA’ed from the Am79C976
controller’s receive FIFO into the system memory.
When the receive FIFO is empty and the Am79C976
device does not own two descriptors (current and next),
the Receive Descriptor Ring is polled at an interval by
the contents of the TXPOLLINT register (CSR47).
When the Am79C976 device owns two descriptors, the
Receive Descriptor Ring is not polled at all.
Setting LAPPEN (CMD2, bit 2 or CSR3, bit 5) to a 1
modifies the way the controller processes receive de-
scriptors. The Am79C976 controller will use the STP
information to determine where it should begin writing
a receive packet’s data. Note that while in this mode,
the Am79C976 controller can write intermediate packet
data to buffers whose descriptors do not contain STP
bits set to 1. Following the write to the last descriptor
used by a packet, the Am79C976 controller will scan
through the next descriptor entries to locate the next
STP bit that is set to a 1. The Am79C976 controller will
begin writing the next packet’s data to the buffer
pointed to by that descriptor.
Note that because several descriptors may be allo-
cated by the host for each packet and not all messages
may need all of the descriptors that are allocated be-
tween descriptors containing STP = 1, then some de-
scriptors/buffers may be skipped in the ring. While
performing the search for the next STP bit that is set to
1, the Am79C976 controller will advance through the
receive descriptor ring regardless of the state of own-
ership bits. If any of the entries that are examined dur-
ing this search indicate Am79C976 controller
ownership of the descriptor but also indicate STP = 0,
then the Am79C976 controller will reset the OWN bit to
0 in these entries. If a scanned entry indicates host
ownership with STP = 0, then the Am79C976 controller
will not alter the entry, but will advance to the next entry.
When the STP bit is found to be true, but the descriptor
that contains this setting is not owned by the
Am79C976 controller, then the Am79C976 controller
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