AM79C976 Advanced Micro Devices, AM79C976 Datasheet - Page 49

• Manufacturer Part Number: AM79C976
• Description: PCnet-PRO 10/100 Mbps PCI Ethernet Controller
• Manufacturer: Advanced Micro Devices

If the controller is executing a Memory Write and Inval-
idate instruction when preemption occurs, the control-
ler will finish writing the current cache line before it
releases the bus.
Figure 19 assumes that the PCI Latency Timer has
counted down to 0 on clock 7.
The Am79C976 controller will terminate its cycle with a
Master Abort sequence if DEVSEL is not asserted
within 4 clocks after FRAME is asserted. Master Abort
is treated as a fatal error by the Am79C976 controller.
The Am79C976 controller will reset all CSR locations
to their STOP_RESET values. The BCR and PCI con-
figuration registers will not be cleared. Any on-going
8/01/00
DEVSEL
FRAME
TRDY
C/BE
IRDY
REQ
GNT
PAR
CLK
AD
1
DEVSEL is sampled
P R E L I M I N A R Y
2
ADDR
Am79C976
0111
3
PAR
network transmission is terminated in an orderly se-
quence. The message will have the current FCS in-
verted and appended at the next byte boundary to
guarantee that the receiving station will treat the trans-
mission either as a runt or as a corrupted frame.
RMABORT (in the PCI Status register, bit 13) will be set
to indicate that the Am79C976 controller has termi-
nated its transaction with a master abort. In addition,
SINT (CSR5, bit 11) will be set to 1. When SINT is set,
INTA is asserted if the enable bit SINTE (CSR5, bit 10)
is set to 1. This mechanism can be used to inform the
driver of the system error. The host can read the PCI
Status register to determine the exact cause of the in-
terrupt. See Figure 2020.
4
DATA
BE
5
PAR
6
7
22929B20
49