AM79C976 Advanced Micro Devices, AM79C976 Datasheet - Page 63

• Manufacturer Part Number: AM79C976
• Description: PCnet-PRO 10/100 Mbps PCI Ethernet Controller
• Manufacturer: Advanced Micro Devices

Note that in this mode the value of CSR2, bits 15-8, is
used as the upper 8-bits for all memory addresses dur-
ing bus master transfers.
If there is no network channel activity and there is no
pre- or post-receive or pre- or post-transmit activity
being performed by the Am79C976 controller, then the
Am79C976 controller will periodically poll the current
receive and transmit descriptor entries in order to as-
certain their ownership. If the TXDPOLL bit in CSR4 is
set, then the transmit polling function is disabled. The
Descriptor Management Unit (DMU) is responsible for
these operations.
The Am79C976 controller stores internally the informa-
tion from two or more receive descriptors and two or
more transmit descriptors. Polling operations depend
on the ownership of the current and next receive and
transmit descriptors.
8/01/00
TLE RES RLE RES
IADR[31:16]
CSR2
RES
Initialization
LADRF[63:32]
LADRF[31:0]
RDRA[31:0]
PADR[31:0]
TDRA[31:0]
Block
PADR[47:32]
IADR[15:0]
CSR1
MODE
P R E L I M I N A R Y
Am79C976
Buffers
Buffers
Xmt
Rcv
1st
desc.
start
RMD0
1st
desc.
start
Figure 29 illustrates the relationship between the initial-
ization base address, the initialization block, the re-
ceive and transmit descriptor ring base addresses, the
receive and transmit descriptors, and the receive and
transmit data buffers, when SSIZE32 is set to 1.
descriptor is not owned by the Am79C976 controller or
if the current receive descriptor is owned and the next
receive descriptor is not owned, the unowned descrip-
tor will be polled. Depending on the software style,
more than one descriptor may be read in a burst.
If the TXDPOLL bit is not set and the poll time has
elapsed, or whenever the TDMD bit is set, if the current
transmit descriptor is not owned by the Am79C976
controller, it will be polled. Depending on the software
style, more than one descriptor may be read in a burst.
disabled due to the setting of TX_SPND, RX_SPND,
SPND, DRX or DTX, the corresponding descriptors will
not be polled. Polling is not affected by fast suspend.
When the poll time has elapsed, if the current receive
If either transmit or receive or both are suspended or
TMD0
Buffer
Buffer
Data
Data
RMD1
1
1
Rcv Descriptor
TMD1 TMD2 TMD3
N
Xmt Descriptor
M
Ring
RMD2 RMD3
Ring
Buffer
Buffer
N
Data
Data
2
2
M
N
M
2nd
desc.
start
2nd
desc.
start
RMD0
N
TMD0
M
•
Buffer
Buffer
Data
Data
•
•
N
M
•
•
•
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