AM79C976 Advanced Micro Devices, AM79C976 Datasheet - Page 301
![no-image](/images/manufacturer_photos/0/0/14/advanced_micro_devices_sml.jpg)
AM79C976
Manufacturer Part Number
AM79C976
Description
PCnet-PRO 10/100 Mbps PCI Ethernet Controller
Manufacturer
Advanced Micro Devices
Datasheet
1.AM79C976.pdf
(309 pages)
- Current page: 301 of 309
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8/01/00
BCR37
BCR38
BCR39
BCR4
BCR40
BCR41
BCR42
BCR43
BCR44
BCR45
BCR46
BCR47
BCR5
BCR6
BCR7
BCR9
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . .4
Board Interface . . . . . . . . . . . . . . . . . . . . . . . 26
Boot ROM Chip Select . . . . . . . . . . . . . . . . .29
Boundary Scan Circuit . . . . . . . . . . . . . . . .103
Boundary Scan Register . . . . . . . . . . . . . . .104
BSR Mode Of Operation . . . . . . . . . . . . . . .104
Buffer Size Tuning . . . . . . . . . . . . . . . . . . .A-7
Burst Write Transfer . . . . . . . . . . . . . . . . . . .45
Bus Acquisition . . . . . . . . . . . . . . . . . . . .40, 41
PCI DATA Register Zero (DATA0)
Alias Register . . . . . . . . . . . . . . . . . . . . . .221
PCI DATA Register One (DATA1)
Alias Register . . . . . . . . . . . . . . . . . . . . . .221
PCI DATA Register Two (DATA2)
Alias Register . . . . . . . . . . . . . . . . . . . . . .221
LED 0 Status . . . . . . . . . . . . . . . . . . . . . .199
PCI Data Register Three (DATA3)
Alias Register . . . . . . . . . . . . . . . . . . . . . .222
PCI DATA Register Four (DATA4)
Alias Register . . . . . . . . . . . . . . . . . . . . . .222
PCI DATA Register Five (DATA5)
Alias Register . . . . . . . . . . . . . . . . . . . . . .222
PCI DATA Register Six (DATA6)
Alias Register . . . . . . . . . . . . . . . . . . . . . .223
PCI DATA Register Seven (DATA7)
Alias Register . . . . . . . . . . . . . . . . . . . . . .223
OnNow Pattern Matching Register #1 . . .223
OnNow Pattern Matching Register #2 . . .224
OnNow Pattern Matching Register #3 . . .224
LED1 Status . . . . . . . . . . . . . . . . . . . . . . .201
LED2 Status . . . . . . . . . . . . . . . . . . . . . . .203
LED3 Status . . . . . . . . . . . . . . . . . . . . . . .205
Full-Duplex Control . . . . . . . . . . . . . . . . .207
P R E L I M I N A R Y
Am79C976
C
Bus Command and Byte Enables . . . . . . . . .24
Bus Configuration Registers . . . .197, 252, 264
Bus Grant . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Bus Master DMA Transfers . . . . . . . . . . . . .40
Bus Request . . . . . . . . . . . . . . . . . . . . . . . . . . 25
C/BE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Carrier Sense . . . . . . . . . . . . . . . . . . . . . . . . 29
CHIPID
CHPOLLTIME
CLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
CLK Waveform for 3.3 V Signaling . . . . . .272
CLK Waveform for 5 V Signaling . . . . . . .272
CLKSEL1 . . . . . . . . . . . . . . . . . . . . . . . . . . .27
CLKSEL2 . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Clock Select 1 . . . . . . . . . . . . . . . . . . . . . . . .27
Clock Select 2 . . . . . . . . . . . . . . . . . . . . . . . .27
Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . 269
CMD0
CMD2
CMD3
CMD7
COL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Collision . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Collision Handling . . . . . . . . . . . . . . . . . . . . 68
command style access . . . . . . . . . . . . . . . . . 122
Connection Diagram (PQR208) . . . . . . . . . .18
Control and Status Registers . . . .173, 248, 262
Control Register (Register 0) . . . . . . . . . . . B-1
CRS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
CSR0
CSR1
CSR10
CSR100
CSR101-111
CSR11
Chip ID Register . . . . . . . . . . . . . . . . . . . . 129
Chain Poll Timer Register 1 . . . . . . . . . . . 29
Command0 . . . . . . . . . . . . . . . . . . . . . . . . 130
Command2 . . . . . . . . . . . . . . . . . . . . . . . . 131
Command3 . . . . . . . . . . . . . . . . . . . . . . . . 135
Command7 . . . . . . . . . . . . . . . . . . . . . . . . 138
Controller Status and Control Register . . 173
Initialization Block Address 0 . . . . . . . . .175
Logical Address Filter 2 . . . . . . . . . . . . .184
Bus Timeout . . . . . . . . . . . . . . . . . . . . . . . 193
Reserved 1 . . . . . . . . . . . . . . . . . . . . . . . .93
Logical Address Filter 3 . . . . . . . . . . . . .184
INDEX-2
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