AM79C976 Advanced Micro Devices, AM79C976 Datasheet - Page 115

• Manufacturer Part Number: AM79C976
• Description: PCnet-PRO 10/100 Mbps PCI Ethernet Controller
• Manufacturer: Advanced Micro Devices

Offset 0Ch
This register indicates the system cache line size in
units of 32-bit double words. This quantity is used to
determine when to use the advanced PCI bus com-
mands (MWI, MRL, and MRM). It is also used for align-
ing PCI burst transfers to cache line boundaries. Only
the values 4, 8, and 16 are acceptable. If the host CPU
attempts to write any other value to this location, the
contents of the register will be set to 0.
This register is cleared by H_RESET and is not effected
by S_RESET or by setting the STOP bit.
Offset 0Dh
The PCI Latency Timer register is an 8-bit register that
specifies the minimum guaranteed time the Am79C976
controller will control the bus once it starts its bus mas-
tership period. The time is measured in clock cycles.
Every time the Am79C976 controller asserts FRAME at
the beginning of a bus mastership period, it will copy the
value of the PCI Latency Timer register into a counter
and start counting down. The counter will freeze at 0.
When the system arbiter removes GNT while the
counter is non-zero, the Am79C976 controller will con-
tinue with its data transfers. It will only release the bus
when the counter has reached 0.
The PCI Latency Timer is only significant in burst trans-
actions, where FRAME stays asserted until the last data
phase. In a non-burst transaction, FRAME is only as-
serted during the address phase. The internal latency
counter will be cleared and suspended while FRAME is
deasserted.
The six most significant bits of the PCI Latency Timer
register are programmable. The two least significant bits
are fixed at 0. The host should read the Am79C976 PCI
MIN_GNT and PCI MAX_LAT registers to determine the
latency requirements for the device and then initialize
the Latency Timer register with an appropriate value.
The PCI Latency Timer register is read and written by
the host. The PCI Latency Timer register is cleared by
H_RESET and is not affected by S_RESET or by setting
the STOP bit.
Offset 0Eh
The PCI Header Type register is an 8-bit register that
describes the format of the PCI Configuration Space
locations 10h to 3Ch and that identifies a device to be
single or multi-function. The PCI Header Type register
is located at address 0Eh in the PCI Configuration
Space. It is read only.
8/01/00
P R E L I M I N A R Y
Am79C976
Bit
7
6-0
Offset 10h
The PCI I/O Base Address register is a 32-bit register
that determines the location of the Am79C976 I/O re-
sources in all of I/O space.
Bit
31-5
4-2
Name
FUNCT
LAYOUT
Name
IOBASE
IOSIZE
When the Am79C976 controller
is enabled for I/O mode (IOEN is
set), it monitors the PCI bus for a
valid I/O command. If the value
on AD[31:5] during the address
phase of the cycles matches the
value of IOBASE, the Am79C976
controller will drive DEVSEL indi-
cating it will respond to the
access.
IOBASE is read and written by
the host. IOBASE is cleared by
H_RESET and is not affected by
S_RESET or by setting the STOP
bit.
IOSIZE indicates the size of the
I/O space the Am79C976 control-
Single-function/multi-function de-
vice. Read as zero; write opera-
tions
Am79C976 controller is a single
function device.
Read as zeros; write operations
have no effect. The layout of the
PCI configuration space loca-
tions 10h to 3Ch is as shown in
the table at the beginning of this
section.
27 bits. These bits are written by
the host to specify the location of
the Am79C976 I/O resources in
all of I/O space. IOBASE must be
written with a valid address be-
fore the Am79C976 controller
slave I/O mode is turned on by
setting the IOEN bit (PCI Com-
mand register, bit 0).
zeros; write operations have no
effect.
Description
PCI configuration space layout.
Description
I/O base address most significant
I/O size requirements. Read as
have
no
effect.
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The