AM79C976 Advanced Micro Devices, AM79C976 Datasheet - Page 107

• Manufacturer Part Number: AM79C976
• Description: PCnet-PRO 10/100 Mbps PCI Ethernet Controller
• Manufacturer: Advanced Micro Devices

address of the memory space. The MEMEN bit in the
PCI Command register must also be set to enable the
mode. Both base address registers can be active at the
same time.
The Am79C976 controller requires that the memory
space that it claims must be within the 32-bit address
space.
The Am79C976 controller supports two modes for ac-
cessing the I/O resources. For backwards compatibility
with AMD’s 16-bit Ethernet controllers, Word I/O is the
default mode after power up. The device can be config-
ured to DWord I/O mode by software.
The Am79C976 controller registers are divided into
three groups: memory-mapped registers, Control and
Status Registers (CSRs), and Bus Control Registers
(BCRs). The CSRs and BCRs are included in the
Am79C976 device for software compatibility with older
PCnet family controllers that do not have the memory-
mapped register group. The CSRs and BCRs are ad-
dressed indirectly through the Register Address Port
(RAP), Register Data Port (RDP), and BCR Data Port
(BDP) so that a large number of functions can be con-
trolled through a small amount of I/O space.
All CSR and BCR functions can be accessed more ef-
ficiently through the memory-mapped registers. The
memory-mapped registers are directly addressed as
offsets from the address stored in the Memory Mapped
I/O Base Address Register, which is located in PCI
Configuration Space.
The Control and Status Registers (CSR) are used to
configure the Ethernet MAC engine and to obtain sta-
tus information. The Bus Control Registers (BCR) are
used to configure the bus interface unit and the LEDs.
Both sets of registers are accessed using indirect ad-
dressing.
The CSR and BCR share a common Register Address
Port (RAP). There are, however, separate data ports.
The Register Data Port (RDP) is used to access a
CSR. The BCR Data Port (BDP) is used to access a
BCR.
In order to access a particular CSR location, the RAP
should first be written with the appropriate CSR ad-
dress. The RDP will then point to the selected CSR. A
read of the RDP will yield the selected CSR data. A
write to the RDP will write to the selected CSR. In order
to access a particular BCR location, the RAP should
first be written with the appropriate BCR address. The
BDP will then point to the selected BCR. A read of the
BDP will yield the selected BCR data. A write to the
BDP will write to the selected BCR.
Once the RAP has been written with a value, the RAP
value remains unchanged until another RAP write oc-
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P R E L I M I N A R Y
Am79C976
curs, or until an H_RESET or S_RESET occurs. RAP
is cleared to all 0s when an H_RESET or S_RESET oc-
curs. RAP is unaffected by setting the STOP bit.
Software written for early PCnet family products ex-
pects the 48-bit IEEE MAC address to be found in a
small external PROM that occupies the first 16 bytes of
the controller’s I/O address space. The software copies
this address from the PROM into the Initialization Block
in host memory. For compatibility with this software the
Am79C976 controller contains 16-bytes of read/write
memory starting at offset 0 in the device’s I/O or mem-
ory address space. This 16 bytes of space is known as
the Address PROM Space (APROM). If compatibility
with this software is required, the EEPROM should load
the data shown in Table 21 into the Address PROM
Space. The order of bytes in the MAC address is such
that the first byte transmitted is located at offset 0.
CPU access to the APROM space is controlled by the
APROM Write Enable (APROMWE) bit (BCR2, bit 8). If
this bit is cleared to 0, the host CPU can not write to the
APROM space. However, the APROM space can be
loaded from the EEPROM regardless of the state of
APROMWE.
A read of the Reset register creates an internal soft-
ware reset (S_RESET) pulse in the Am79C976 control-
ler. The effect of this reset is the same as that of setting
the STOP bit, except that S_RESET clears some bits
that are not affected by setting STOP.
This register exists for backward compatibility with ear-
lier PCnet family devices. It should not be used in new
software.
The NE2100 LANCE-based family of Ethernet cards
requires that a write access to the Reset register fol-
lows each read access to the Reset register. The
Am79C976 controller does not have a similar require-
ment. The write access is not required and does not
have any effect.
Table 21. Address PROM Space Contents
0Ch-0Dh
06h-0Bh
0Eh-0Fh
00h-05h
Offset
Check sum of bytes 0-11 and
00 00 00 00 00 00h
ASCII “W” (57h)
MAC Address
bytes 14-15
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