AM79C976 Advanced Micro Devices, AM79C976 Datasheet - Page 211

• Manufacturer Part Number: AM79C976
• Description: PCnet-PRO 10/100 Mbps PCI Ethernet Controller
• Manufacturer: Advanced Micro Devices

12-5
4
3
2
8/01/00
EEDET Value
(BCR19[13])
High
High
High
Low
Pin
RES
EEN
RES
ECS
0
0
1
1
Read in Progress
*PREAD or Auto
Connected?
Table 90 indicates the possible
combinations of EEDET and the
existence of an EEPROM and the
resulting operations that are pos-
sible on the EEPROM interface.
zeros; read as undefined.
bit is set to a 1, it causes the val-
ues of ECS, ESK, and EDI to be
driven onto the EECS, EESK,
and EEDI pins, respectively. If
EEN = 0 and no EEPROM read
function is currently active, then
EECS will be driven LOW. When
zero and read as undefined.
used to control the value of the
EECS pin of the interface when
the EEN bit is set to 1 and the
PREAD bit is set to 0. If EEN = 1
and PREAD = 0 and ECS is set
to a 1, then the EECS pin will be
forced to a HIGH level at the ris-
ing edge of the next clock follow-
ing bit programming.
Reserved locations. Written as
EEPROM Port Enable. When this
Reserved location. Written as
EEPROM Chip Select. This bit is
EEPROM
X
1
0
0
Yes
Yes
No
No
EEPROM read operation is attempted.
Entire read sequence will occur; checksum
failure will result; PVALID is reset to 0.
EEPROM read operation is attempted.
Entire read sequence will occur; checksum
operation will pass; PVALID is set to 1.
EEPROM read operation is attempted.
Entire read sequence will occur; checksum
failure will result; PVALID is reset to 0.
EEPROM read operation is attempted.
Entire read sequence will occur; checksum
operation will pass; PVALID is set to 1.
Table 91. Interface Pin Assignment
Result if PREAD is Set to 1
EEN
X
X
1
0
P R E L I M I N A R Y
Am79C976
Bit of BCR19
From ECS
EECS
Active
0
0
Table 90. EEDET Setting
First two EESK clock cycles are generated,
then EEPROM read operation is aborted
and PVALID is reset to 0.
First two EESK clock cycles are generated,
then EEPROM read operation is aborted
and PVALID is reset to 0.
EEPROM read operation is attempted.
Entire read sequence will occur; checksum
failure will result; PVALID is reset to 0.
EEPROM read operation is attempted.
Entire read sequence will occur; checksum
operation will pass; PVALID is set to 1.
From ESK Bit of
Result of Automatic EEPROM Read
Operation Following H_RESET
Tri-State
BCR19
EESK
Active
Read/Write accessible. EEN is
set to 0 by H_RESET and is unaf-
fected by S_RESET or STOP.
LED1
If EEN = 1 and PREAD = 0 and
ECS is set to a 0, then the EECS
pin will be forced to a LOW level
at the rising edge of the next
clock following bit programming.
ECS has no effect on the output
value of the EECS pin unless the
PREAD bit is set to 0 and the
EEN bit is set to 1.
Read/Write accessible. ECS is
set to 0 by H_RESET and is not
affected by S_RESET or STOP.
EEN = 0 and no EEPROM read
function is currently active, EESK
and EEDI pins will be driven by
the LED registers BCR5 and
BCR4, respectively. See Table
91.
From EEDI Bit of
Tri-State
BCR19
Active
LED0
EEDI
211