AM79C976 Advanced Micro Devices, AM79C976 Datasheet - Page 136

• Manufacturer Part Number: AM79C976
• Description: PCnet-PRO 10/100 Mbps PCI Ethernet Controller
• Manufacturer: Advanced Micro Devices

136
Bit
19
18
17
16
15
14
13
12
11
RTRY_LCOL
FORCE_FD
REX_RTRY
REX_UFLO
FORCE_LS
INTLEVEL
VLONLY
DISPM
Name
VAL1
Admit Only VLAN Frames. When this bit is set to 1, only frames with a VLAN Tag Header
containing a non-zero VLAN ID field will be received. All other frames will be rejected.
Retransmit on Retry Error. When this bit is set to 1, if collisions occur for 16 attempts to transmit
a frame, the back-off logic is reset, but the frame is not discarded. Instead, it is treated as if it
were the next frame in the transmit queue.
When this bit is cleared to 0, if collisions occur for 16 attempts to transmit a frame, the frame is
dropped.
In either case, if collisions occur for 16 attempts to transmit a frame, the XmtExcessiveCollision
counter is incremented.
Retransmit on Underflow. When this bit is set to 1, if the transmitter is forced to abort a
transmission because the transmit FIFO underflows, the transmitter will not discard the frame.
Instead, it will automatically wait until the entire frame has been loaded into the transmit FIFO
and then will restart the transmission process.
When this bit is cleared to 0, if the transmitter is forced to abort a transmission because the FIFO
underflows, the transmitter will discard the frame.
In either case, the XmtUnderrunPkts counter will be incremented.
Retry on Late Collision. When this bit is set to 1, late collisions are treated like normal collisions,
except that the XmtLateCollision counter and the XmtCollisions counter will both be incremented.
When this bit is cleared to 0, if a late collision occurs, the transmitter will discard the frame that
was being transmitted when the collision occurred.
Value bit for byte 1. The value of this bit is written to any bits in the CMD3 register that correspond
to bits in the CMD3[14:8] bit map field that are set to 1.
Disable Port Manager. (The corresponding bit in older PCnet family devices is called Disable
Auto-Negotiation Auto Setup or DANAS. The name has been changed, but not the function.)
When DISPM is set, the Network Port Manager function is disabled, and the host CPU is
responsible for ensuring that the MAC and external PHY are operating in the same mode.
This bit is an alias of BCR32, bit 7.
Interrupt Level. This bit allows the interrupt output signals to be programmed for level- or edge-
sensitive applications.
When INTLEVEL is cleared to 0, the INTA pin is configured for level-sensitive applications. In this
mode, an interrupt request is signaled by a low level driven on the INTA pin by the Am79C976
controller. When the interrupt is cleared, the INTA pin is tri-stated by the Am79C976 controller
and allowed to be pulled to a high level by an external pull-up device. This mode is intended for
systems which allow the interrupt signal to be shared by multiple devices.
When INTLEVEL is set to 1, the INTA pin is configured for edge-sensitive applications. In this
mode, an interrupt request is signaled by a high level driven on the INTA pin by the Am79C976
controller. When the interrupt is cleared, the INTA pin is driven to a low level by the Am79C976
controller. This mode is intended for systems that do not allow interrupt channels to be shared by
multiple devices.
INTLEVEL should not be set to 1 when the Am79C976 controller is used in a PCI bus application.
This bit is an alias of BCR2, bit 7.
Force Full Duplex. (This bit is called Full-Duplex Enable (FDEN) in other PCnet family devices.)
This bit controls whether full-duplex operation is enabled. When FORCE_FD is cleared and the
Port Manager is disabled, the Am79C976 controller will always operate in the half-duplex mode.
When FORCE_FD is set, the Am79C976 controller will operate in full-duplex mode. Do not set
this bit when the Port Manager is enabled.
This bit is an alias of BCR9, bit 0.
Force Link Status. When this bit is set, the internal link status is forced to the Pass state
regardless of the actual state of the PHY device. When this bit is cleared to 0, the internal link
status is determined by the Port Manager.
P R E L I M I N A R Y
Am79C976
Description
8/01/00