AM79C976 Advanced Micro Devices, AM79C976 Datasheet - Page 243

• Manufacturer Part Number: AM79C976
• Description: PCnet-PRO 10/100 Mbps PCI Ethernet Controller
• Manufacturer: Advanced Micro Devices

8/01/00
Offset
Offset
0Ch
4
8
0
0
0
0
0
0
0
0
0
0
27-26
21-16
15-0
31-0
31-0
Bit
Bit
31
30
29
28
25
24
23
22
USER SPACE
TBADR[31:0]
ADD_FCS
TCI[15:0]
Name
Name
LTINT
OWN
ENP
KILL
STP
Tag Control Information. If the contents of the TCC field is 10 or 11, the controller will
transmit the contents of the TCI field as bytes 15 and 16 of the outgoing frame.
Transmit Buffer Address. This field contains the address of the Transmit buffer that is
associated with this descriptor.
User Space. Reserved for user defined data.
This bit indicates whether the descriptor entry is owned by the host (OWN = 0) or by
the Am79C976 controller (OWN = 1). The host sets the OWN bit after filling the buffer
pointed to by the descriptor entry. The Am79C976 controller clears the OWN bit after
transmitting the contents of the buffer. Both the Am79C976 controller and the host
must not alter a descriptor entry after it has relinquished ownership.
Reserved location
ADD_FCS dynamically controls the generation of FCS on a frame by frame basis.
This bit should be set with the ENP bit. However, for backward compatibility, it is
recommended that this bit be set for every descriptor of the intended frame. When
ADD_FCS is set, the state of DXMTFCS is ignored and transmitter FCS generation is
activated. When ADD_FCS is cleared to 0, FCS generation is controlled by
DXMTFCS. When APAD_XMT (CSR4, bit 11) is set to 1, the setting of ADD_FCS has
no effect. ADD_FCS is set by the host, and is not changed by the Am79C976
controller. This is a reserved bit in the C-LANCE (Am79C90) controller.
Last Transmit Interrupt. When enabled by the LTINTEN bit (CSR5, bit 14), LTINT is
used to suppress interrupts after selected frames have been copied to the transmit
FIFO. When LTINT is cleared to 0 and ENP is set to 1, the Am79C976 controller will
not set TINT (CSR0, bit 9) after the corresponding frame has been copied to the
transmit FIFO. TINT will only be set when the last descriptor of a frame has both LTINT
and ENP set to 1. When LTINTEN is cleared to 0, the LTINT bit is ignored.
Reserved.
Start of Packet indicates that this is the first buffer to be used by the Am79C976
controller for this frame. It is used for data chaining buffers. The STP bit must be set
in the first buffer of the frame, or the Am79C976 controller will skip over the descriptor
and poll the next descriptor(s) until the OWN and STP bits are set. STP is set by the
host and is not changed by the Am79C976 controller.
End of Packet indicates that this is the last buffer to be used by the Am79C976
controller for this frame. It is used for data chaining buffers. If both STP and ENP are
set, the frame fits into one buffer and there is no data chaining. ENP is set by the host
and is not changed by the Am79C976 controller.
Reserved.
This bit causes the transmission of the corresponding frame to be aborted. If the
transmitter has not started sending the frame at the time that the descriptor
processing logic encounters the KILL bit, no portion of the frame will be sent. If part
of the frame has been sent, the frame will be truncated, and an FCS field containing
the inverse of the correct CRC will be appended.
Reserved.
P R E L I M I N A R Y
Am79C976
.
Description
Description
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