AM79C976 Advanced Micro Devices, AM79C976 Datasheet - Page 199

• Manufacturer Part Number: AM79C976
• Description: PCnet-PRO 10/100 Mbps PCI Ethernet Controller
• Manufacturer: Advanced Micro Devices

Note: Bits 15-0 in this register are programmable
through the EEPROM.
Bit
31-16
15-13
12
11-9
8
7
8/01/00
Name
RES
RES
LEDPE
RES
APROMWE Address PROM Write Enable.
INTLEVEL
zeros and read as undefined.
read as zeros.
LEDPE is set to 1, programming
of the LED0 (BCR4), LED1
(BCR5),
LED3 (BCR7) registers is en-
abled. When LEDPE is cleared to
0, programming of LED0 (BCR4),
LED1 (BCR5), LED2 (BCR6),
and LED3 (BCR7) registers is
disabled. Writes to those regis-
ters will be ignored.
Read/Write accessible. LEDPE is
cleared to 0 by H_RESET and is
unaffected by S_RESET or by
setting the STOP bit.
read as zeros.
The Am79C976 controller con-
tains a shadow RAM on board for
storage of the first 16 bytes load-
ed from the serial EEPROM.
Accesses to Address PROM I/O
Resources will be directed to-
ward this RAM. When APROM-
WE is set to 1, then write access
to the shadow RAM will be en-
abled.
Read/Write accessible. APROM-
WE is cleared to 0 by H_RESET
and is unaffected by S_RESET or
by setting the STOP bit.
interrupt output signals to be pro-
grammed for level or edge-
sensitive applications.
When INTLEVEL is cleared to 0,
the INTA pin is configured for
level-sensitive applications. In
this mode, an interrupt request is
signaled by a low level driven on
Reserved locations. Written as
Reserved locations. Written and
LED Program Enable. When
Reserved locations. Written and
Interrupt Level. This bit allows the
Description
LED2
(BCR6),
P R E L I M I N A R Y
and
Am79C976
6-4
3
2
1
0
BCR4 controls the function(s) that the LED0 pin dis-
plays. Multiple functions can be simultaneously en-
abled on this LED pin. The LED display will indicate the
logical OR of the enabled functions. BCR4 defaults to
Link Status (LNKST) with pulse stretcher enabled
(PSE = 1) and is fully programmable.
Note: When LEDPE (BCR2, bit 12) is set to 1, pro-
gramming of the LED0 Status register is enabled.
RES
EADISEL
RES
ASEL
RES
the INTA pin by the Am79C976
controller. When the interrupt is
cleared, the INTA pin is tri-stated
by the Am79C976 controller and
allowed to be pulled to a high lev-
el by an external pull-up device.
This
systems which allow the interrupt
signal to be shared by multiple
devices.
When INTLEVEL is set to 1, the
INTA pin is configured for edge-
sensitive applications. In this
mode, an interrupt request is sig-
naled by a high level driven on
the INTA pin by the Am79C976
controller. When the interrupt is
cleared, the INTA pin is driven to
a low level by the Am79C976
controller. This mode is intended
for systems that do not allow
interrupt channels to be shared
by multiple devices.
INTLEVEL should not be set to 1
when the Am79C976 controller is
used in a PCI bus application.
Read/Write accessible. INTLEV-
EL is cleared to 0 by H_RESET
and is unaffected by S_RESET or
by setting the STOP bit.
zeros and read as undefined.
effect. Read as undefined.
read as zeros.
effect. Read as undefined.
read as zeros.
Reserved locations. Written as
Obsolete function. Writing has no
Reserved location. Written and
Obsolete function. Writing has no
Reserved location. Written and
mode
is
intended
199
for