AM79C976 Advanced Micro Devices, AM79C976 Datasheet - Page 196

• Manufacturer Part Number: AM79C976
• Description: PCnet-PRO 10/100 Mbps PCI Ethernet Controller
• Manufacturer: Advanced Micro Devices

2-0
Bit
31-16
15-8
196
RES
Name
RES
IPG
Read/Write accessible. RPA is
cleared
S_RESET and is not affected by
STOP.
zeros and read as undefined.
zeros and read as undefined.
cates the minimum number of
network bit times after the end of
a frame that the transmitter will
wait before it starts transmitting
another frame.
mode the end of the frame is de-
termined by CRS, while in full-du-
plex mode the end of the frame is
determined by TX_EN. The IPG
value can be adjusted to com-
pensate for delays through the
external PHY device.
IPG should be programmed to
the nearest nibble. The two least
significant bits are ignored. For
example, programming IPG to
63h has the same effect as pro-
gramming it to 60h.
Reserved locations. Written as
Reserved locations. Written as
Inter Packet Gap. This value indi-
Description
by
H_RESET
In half-duplex
P R E L I M I N A R Y
Am79C976
or
7-0
IFS1
CAUTION: Use this parameter
with care. By lowering the IPG
below the IEEE 802.3 standard
96 bit times, the Am79C976 con-
troller can interrupt normal net-
work behavior.
Read/Write accessible. IPG is set
to
H_RESET or S_RESET and is
not affected by STOP.
IFS1 = IPG - 36 bit times
IPG should be programmed to
the nearest nibble. The two least
significant bits are ignored. For
example, programming IPG to
63h has the same effect as pro-
gramming it to 60h.
Read/Write accessible. IFS1 is
set to 3ch (60 bit times) by
H_RESET or S_RESET and is
not affected by STOP.
Changing IFS1 allows the user to
program the value of the Inter-
Frame-SpacePart1 timing. The
Am79C976 controller sets the de-
fault value at 60 bit times (3ch).
See the subsection on Medium
Allocation in the section Media
Access Management for more
details. The equation for setting
IFS1 when IPG ˜ 96 bit times is:
InterFrameSpacingPart1.
60h
(96
Bit
times)
8/01/00
by