AM79C976 Advanced Micro Devices, AM79C976 Datasheet - Page 42

• Manufacturer Part Number: AM79C976
• Description: PCnet-PRO 10/100 Mbps PCI Ethernet Controller
• Manufacturer: Advanced Micro Devices

The FIFO thresholds should be greater than or equal to
the cache line size to maximize the use of the MRL and
MRM commands. If the PCI bridge stops a transfer, the
Am79C976 device waits until the FIFO threshold con-
ditions are met before resuming the transfer.
During the address phase of a burst access, AD[1:0]
will both be 0 indicating a linear burst order. Note that
during a burst read operation, all byte lanes will always
be active. The Am79C976 controller will internally dis-
card unneeded bytes.
The Am79C976 controller will always perform only a
single burst read transaction per bus mastership pe-
riod, where transaction is defined as one address
ph as e and o ne or mul ti pl e dat a p ha s es. Th e
Am79C976 controller supports zero wait state read cy-
cles. It asserts IRDY immediately after the address
phase and at the same time starts sampling DEVSEL.
FRAME is deasserted when the next-to-last data
phase is completed.
The device may insert IRDY wait states in the middle of
a burst read transaction.
Figure 12 shows a typical burst read access. The
Am79C976 controller arbitrates for the bus, is granted
42
DEVSEL
FRAME
TRDY
C/BE
IRDY
REQ
GNT
PAR
CLK
AD
1
DEVSEL is sampled
2
ADDR
0110
3
P R E L I M I N A R Y
PAR
4
0000
Am79C976
DATA
5
PAR
access, reads three 32-bit words (DWord) from the sys-
tem memory, and then releases the bus. In the exam-
ple, the memory system extends the data phase of
each access by one wait state.
The Am79C976 controller uses non-burst cycles to
write descriptors when SWSTYLE (BCR20, bits 7-0) is
0 or 2. All Am79C976 controller non-burst write ac-
cesses are of the PCI command type Memory Write
(type 7). The byte enable signals indicate the byte
lanes that have valid data.The Am79C976 controller
may perform more than one non-burst write transaction
within a single bus mastership period. FRAME is
dropped between consecutive non-burst write cycles.
REQ, however, stays asserted until FRAME is asserted
for the last transaction. The Am79C976 supports zero
wait state write cycles. (See the section Descriptor
DMA Transfers for the only exception.) It asserts IRDY
immediately after the address phase.
Figure 13 shows two non-burst write transactions. The
first transaction has two wait states. The Am79C976
device supports zero wait state non-burst write cycles.
6
ADDR
0110
7
PAR
8
0000
9
DATA
10
PAR
11
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