AM79C976 Advanced Micro Devices, AM79C976 Datasheet - Page 138
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AM79C976
Manufacturer Part Number
AM79C976
Description
PCnet-PRO 10/100 Mbps PCI Ethernet Controller
Manufacturer
Advanced Micro Devices
Datasheet
1.AM79C976.pdf
(309 pages)
- Current page: 138 of 309
- Download datasheet (3Mb)
CMD7: Command7
Offset 064h
CMD7 is a command-style register. All bits in this reg-
ister are cleared to 0 when power is first applied to the
device (power-on reset). The contents of this register
138
31-8
Bit
6-4
7
3
2
1
0
LCMODE_SW
PMAT_MODE
MPPEN_SW
MPEN_SW
Name
VAL0
RES
RES
Reserved locations. Written as zeros and read as undefined.
Value bit for byte 0. The value of this bit is written to any bits in the CMD7 register that correspond
to bits in the CMD7[6:0] bit map field that are set to 1.
Reserved locations. Written as zeros and read as undefined.
Pattern Match Mode. Writing a 1 to this bit will enable Pattern Match Mode and should only be done
after the Pattern Match RAM has been programmed.
Pattern Match Mode is enabled when either this bit or BCR45, bit 7 is set.
Magic Packet Pin Enable. When either this bit or the MPPEN_EE bit in CMD3 is set, the device
enters the Magic Packet mode when the PG input goes LOW. This bit has the same function as
MPPEN_EE except that H_RESET clears MPPEN_EE to 0, while H_RESET has no effect on
MPPEN_SW.
Magic Packet Software Mode Enable. The Am79C976 controller enters the Magic Packet mode
when this bit is set to 1. This bit has the same function as MPEN_EE except that H_RESET clears
MPEN_EE to 0, while H_RESET has no effect on MPEN_SW.
Link Change Wake-up Mode. When either this bit or the LCMODE_EE bit in CMD3 is set to 1, the
LCDET bit gets set when the MII auto polling logic detects a Link Change. This bit has the same
function as LCMODE_EE except that H_RESET clears LCMODE_EE to 0, while H_RESET has
no effect on LCMODE_SW.
Table 45.
P R E L I M I N A R Y
CMD7: Command7 Register
Am79C976
are not affected by the state of the RST pin. The con-
tents of this register can not be loaded from the
EEPROM. Therefore, the contents of this register are
not disturbed when PCI bus power is removed and re-
applied.
Description
8/01/00
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