AM79C976 Advanced Micro Devices, AM79C976 Datasheet - Page 175

• Manufacturer Part Number: AM79C976
• Description: PCnet-PRO 10/100 Mbps PCI Ethernet Controller
• Manufacturer: Advanced Micro Devices

Bit
31-16
15-0
Bit
31-16
15-8
8/01/00
Name
RES
IADR[15:0] Lower 16 bits of the address of
Name
RES
IADR[31:24] If SSIZE32 is set (BCR20, bit 8),
no effect. INIT is cleared by
H_RESET, S_RESET, or by set-
ting the STOP bit.
zeros and read as undefined.
the Initialization Block. Bit loca-
tions 1 and 0 must both be 0 to
align the initialization block to a
DWord boundary.
This register is aliased with
CSR16.
Read/Write accessible. Unaffect-
ed by H_RESET or S_RESET, or
by setting the STOP bit.
zeros and read as undefined.
then the IADR[31:24] bits will be
used strictly as the upper 8 bits of
the initialization block address.
However, if SSIZE32 is reset
(BCR20,
IADR[31:24] bits will be used to
generate the upper 8 bits of all
bus mastering addresses, as re-
quired for a 32-bit address bus.
Note that the 16-bit software
structures
SSIZE32 = 0 setting will yield
only 24 bits of address for the
Am79C976 bus master access-
es, while the 32-bit hardware for
which the Am79C976 controller is
intended will require 32 bits of ad-
dress.
SSIZE32 = 0, the IADR[31:24]
bits will be appended to the 24-bit
initialization address, to each 24-
bit descriptor base address and
to each beginning 24-bit buffer
address in order to form complete
32-bit addresses. The upper 8
bits that exist in the descriptor ad-
dress registers and the buffer ad-
Reserved locations. Written as
Reserved locations. Written as
Description
Description
Therefore,
bit
specified
8),
P R E L I M I N A R Y
then
whenever
by
the
the
Am79C976
7-0
Bit
31-16 RES
15-13 RES
12
11
10
IADR[23:16] Bits 23 through 16 of the address
Name
MISSM
MERRM
RINTM
dress registers which are stored
on board the Am79C976 control-
ler will be overwritten with the
IADR[31:24] value, so that CSR
accesses to these registers will
show the 32-bit address that in-
cludes the appended field.
If SSIZE32 = 1, then software will
provide 32-bit pointer values for
all of the shared software struc-
tures - i.e., descriptor bases and
buffer addresses, and therefore,
IADR[31:24] will not be written to
the upper 8 bits of any of these
resources, but it will be used as
the upper 8 bits of the initializa-
tion address.
This register is aliased with
CSR17.
Read/Write accessible. Unaffect-
ed by H_RESET, S_RESET, or
by setting the STOP bit.
Read/Write accessible Unaffect-
ed by H_RESET, S_RESET, or
by setting the STOP bit.
Read/Write accessible. RINTM is
set by H_RESET but cleared by
S_RESET and is not affected by
STOP.
of the Initialization Block. When-
ever this register is written,
CSR17 is updated with CSR2’s
contents.
zeros and read as undefined.
Reserved locations. Read and
written as zero.
effect. Read as undefined.
Obsolete function. Writing has no
effect. Read as undefined.
Receive Interrupt Mask. If RINTM
is set, the RINT bit will be masked
and unable to set the INTR bit.
Description
Reserved locations. Written as
Obsolete function. Writing has no
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