AM79C976 Advanced Micro Devices, AM79C976 Datasheet - Page 123

• Manufacturer Part Number: AM79C976
• Description: PCnet-PRO 10/100 Mbps PCI Ethernet Controller
• Manufacturer: Advanced Micro Devices

Offset 0ACh
The contents of this register are cleared to 0 when the
RST pin is asserted. The register is not cleared at the
start of a serial EEPROM read operation or after a se-
rial EEPROM read error.
Offset 0AEh
The contents of this register are cleared to 0 when the
RST pin is asserted. The register is not cleared at the
start of a serial EEPROM read operation or after a se-
rial EEPROM read error.
Offset 0B0h
The contents of this register are cleared to 0 when the
RST pin is asserted. The register is not cleared at the
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Table 27. AP_VALUE1: Auto-Poll Value1 Register
Table 28. AP_VALUE2: Auto-Poll Value2 Register
Table 29. AP_VALUE3: Auto-Poll Value3 Register
15-0
15-0
15-0
Bit
Bit
Bit
14-13
12-8
Bit
15
AP_VALUE2
AP_VALUE3
AP_VALUE
Name
Name
Name
1
AP_REG0_EN Enable Bit for Autopoll Register 0. This bit is read-only and always has the value 1.
AP_REG0_
This register contains the results of
the automatic polling of the user-
selectable external PHY register,
AP_REG1.
ADDR
This register contains the results of
the automatic polling of the user-
selectable external PHY register,
AP_REG3.
Name
This register contains the results of
the automatic polling of the user-
selectable external PHY register,
AP_REG2.
RES
Description
Description
Description
Reserved locations. Written as zeros and read as undefined
AP_REG0 Address. This field is read-only and always has the value 00001.
Table 32.
P R E L I M I N A R Y
AUTOPOLL0: Auto-Poll0 Register
Am79C976
start of a serial EEPROM read operation or after a se-
rial EEPROM read error.
Offset 0B2h
The contents of this register are cleared to 0 when the
RST pin is asserted. The register is not cleared at the
start of a serial EEPROM read operation or after a se-
rial EEPROM read error.
Offset 088h
This register controls the automatic polling of the status
register of the default external PHY.
All bits in this register are set to their default values by
H_RESET. All bits are also set to their default values
before EEPROM data are loaded or after an EEPROM
read failure.
The default value for all bits except for bits 15
(AP_REG0_EN) and 12:8 (AP_REG0_ADDR) is 0.
The default value for AP_REG0_EN is 1 and the default
value for the AP_REG0_ADDR field is 00001b.
When loading the AUTOPOLL0 register from the EE-
PROM, bits [9:5] are also loaded into BCR33 bits [9:5].
This allows operation with legacy drivers that expect
the PHY address in that location.
Table 30. AP_VALUE4: Auto-Poll Value4 Register
Table 31. AP_VALUE5: Auto-Poll Value5 Register
15-0 AP_VALUE4
15-0 AP_VALUE5
Bit
Bit
Description
Name
Name
This register contains the results of
the automatic polling of the user-
selectable external PHY register,
AP_REG4.
This register contains the results of
the automatic polling of the user-
selectable external PHY register,
AP_REG5.
Description
Description
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