AM79C976 Advanced Micro Devices, AM79C976 Datasheet - Page 83

• Manufacturer Part Number: AM79C976
• Description: PCnet-PRO 10/100 Mbps PCI Ethernet Controller
• Manufacturer: Advanced Micro Devices

agement Frame is a preamble of 32 ones that guaran-
tees that all of the external PHYs are synchronized on
the same interface. (See Figure 3434.) Loss of syn-
chronization is possible due to the hot-plugging capa-
The preamble (if present) is followed by a start field
(ST) and an operation field (OP). The operation field
(OP) indicates whether the Am79C976 controller is ini-
tiating a read or write operation. This field is followed by
the external PHY address (PHYAD) and the register
address (REGAD). The PHY address of 1Fh is re-
served and should not be used.
The register address field is followed by a bus turn-
around field. During a read operation, the bus turn-
around field is used to determine if the external PHY is
responding correctly to the read request or not. The
Am79C976 controller will tri-state the MDIO for both
MDC cycles.
During the second cycle of a read operation, if the ex-
ternal PHY is synchronized to the Am79C976 control-
ler, the external PHY will drive a 0. If the external PHY
does not drive a 0, the Am79C976 controller will signal
a MREINT (CSR7, bit 9) interrupt, if MREINTE (CSR7,
bit 8) is set to a 1. This interrupt indicates that the
Am79C976 controller had an MII management frame
read error and that the data read is not valid.
During a write access the Am79C976 controller drives
a 1 for the first bit time of the turnaround field and a 0
for the second bit time.
After the Turn Around field comes the data field. For a
write access the Am79C976 controller fills this field
with data to be written to the PHY device. For a read ac-
cess the external PHY device fills this field with data
from the selected register.
The last field of the MII Management Frame is an IDLE
field that is necessary to give ample time for drivers to
turn off before the next access.
MII management frames transmitted through the MDIO
pin are synchronized with the rising edge of the Man-
agement Data Clock (MDC). The Am79C976 controller
8/01/00
1111....1111
Preamble
Bits
32
Bits
ST
01
2
10 Rd
01 Wr
OP
Bits
2
P R E L I M I N A R Y
Address
PHY
Bits
5
Am79C976
bility of the exposed MII. The preamble can be
suppressed as described below if the external PHY is
designed to accept frames with no preamble.
will drive the MDC to 0 and tri-state the MDIO anytime
the MII Management Port is not active.
To help to speed up the reading and writing of the MII
management frames to the external PHY, the MDC can
be sped up to 10 MHz by setting the FMDC bits in
BCR32. The IEEE 802.3 specification requires use of
the 2.5-MHz clock rate, but 5 MHz and 10 MHz are
available for the user. The intended applications are
that the 10-MHz clock rate can be used for a single ex-
ternal PHY on an adapter card or motherboard. The
5-MHz clock rate can be used for an exposed MII with
one external PHY attached. The 2.5-MHz clock rate is
intended to be used when multiple external PHYs are
connected to the MII Management Port or if compli-
ance to the IEEE 802.3u standard is required.
The host CPU can indirectly read and write external
PHY registers through the PHY Access Register or, for
compatibility with other PCnet family devices, through
BCR33 and BCR34.
To write to a PHY register the host CPU puts the regis-
ter data into the PHY_DATA field of the PHY Access
Register, specifies the address of the external PHY de-
vice in the PHY_ADDR field and the PHY register num-
ber in the PHY_REG_ADDR field, and sets the
PHY_WR_CMD bit.
The Am79C976 device provides two types of read ac-
cess to external PHY registers, blocking and non-block-
ing. If a blocking read access is used, the device will
generate PCI disconnect/retry cycles if the host CPU
attempts to read the PHY Access Register while the
MII Management Frame is being processed. If a non-
blocking read is used, the PHY Access Register can be
read at any time, and the PHY_CMD_DONE bit in that
register indicates whether or not PHY_DATA field con-
tains valid data.
Register
Address
Bits
5
Z0 Rd
10 Wr
Bits
TA
2
Data
Bits
16
Idle
Bit
1
Z
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