AM79C976 Advanced Micro Devices, AM79C976 Datasheet - Page 179

• Manufacturer Part Number: AM79C976
• Description: PCnet-PRO 10/100 Mbps PCI Ethernet Controller
• Manufacturer: Advanced Micro Devices

1-0
Certain bits in CSR5 indicate the cause of an interrupt.
The register is designed so that these indicator bits are
cleared by writing ones to those bit locations. This
means that the software can read CSR5 and write back
the value just read to clear the interrupt condition.
Bit
31-16
15
14
13
8/01/00
RES
Name
RES
TOKINTD
LTINTEN
TXDNINT
zeros and read as undefined.
zeros and read as undefined.
effect. Read as undefined.
When this bit is set to 1, the
LTINT bit in transmit descriptors
can be used to determine when
transmit interrupts occur. The
Transmit Interrupt (TINT) bit will
be set after a frame has been
copied to the Transmit FIFO if the
LTINT bit in the frame’s last
transmit descriptor is set. If the
LTINT bit in the frame’s last de-
scriptor is 0 TINT will not be set
after the frame has been copied
to the Transmit FIFO.
Read/Write accessible. LTINTEN
is cleared by H_RESET or
S_RESET and is unaffected by
STOP.
This bit is set when the transmit-
ter has finished sending a frame.
This bit is included for debugging
purposes.
Read/Write accessible. TXDN-
INT is cleared by the host by writ-
ing a 1. Writing a 0 has no effect.
The state of TXDNINT is not af-
fected by clearing any of the PCI
Status register bits that get set
when
(DATAPERR, bit 8), master abort
(RMABORT, bit 13), or target
abort (RTABORT, bit 12) occurs.
TXDNINT
H_RESET, S_RESET, or by set-
ting the STOP bit.
Reserved locations. Written as
Reserved locations. Written as
Obsolete function. Writing has no
Last Transmit Interrupt Enable.
Transmission
Description
a
data
is
Done
cleared
parity
P R E L I M I N A R Y
Interrupt.
error
Am79C976
by
12
11
10
9-8
7
TXDNINTEN Transmission Done Interrupt En-
SINT
SINTE
RES
EXDINT
Read/Write accessible. TXDN-
INTEN is cleared by H_RESET or
S_RESET and is unaffected by
STOP.
When SINT is set, INTA is assert-
ed if the enable bit SINTE is 1.
Note that the assertion of an in-
terrupt due to SINT is not depen-
dent on the state of the INEA bit,
since INEA is cleared by the
STOP reset generated by the
system error.
Read/Write accessible. SINT is
cleared by the host by writing a 1.
Writing a 0 has no effect. The
state of SINT is not affected by
clearing any of the PCI Status
register bits that get set when a
data parity error (DATAPERR, bit
8), master abort (RMABORT, bit
13), or target abort (RTABORT,
bit 12) occurs. SINT is cleared by
H_RESET or S_RESET and is
not affected by setting the STOP
bit.
Read/Write accessible. SINTE is
set
S_RESET and is not affected by
setting the STOP bit.
able. When this bit is set, the
INTR bit will be set when the
TXDNINT bit in INT0 is set.
Am79C976 controller when it de-
tects a system error during a bus
master transfer on the PCI bus.
System errors are data parity er-
ror, master abort, or a target
abort. The setting of SINT due to
data parity error is not dependent
on the setting of PERREN (PCI
Command register, bit 6).
System Interrupt Enable. If SIN-
TE is set, the SINT bit will be able
to set the INTR bit.
zeros and read as undefined.
Obsolete function. Writing has no
effect. Read as undefined.
System Interrupt is set by the
Reserved locations. Written as
to
0
by
H_RESET
179
or