AM79C976 Advanced Micro Devices, AM79C976 Datasheet - Page 174

• Manufacturer Part Number: AM79C976
• Description: PCnet-PRO 10/100 Mbps PCI Ethernet Controller
• Manufacturer: Advanced Micro Devices

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IENA
RXON
TXON
TDMD
INTR is read only. INTR is
cleared by clearing all of the ac-
tive individual interrupt bits that
have not been masked out.
be active if the Interrupt Flag is
set. If IENA = 0, then INTA will be
disabled regardless of the state
of INTR.
Read/Write accessible. IENA is
set by writing a 1 and cleared by
writing a 0. IENA is cleared by
H_RESET or S_RESET and set-
ting the STOP bit.
ceive function is enabled. RXON
is set if DRX (CSR15, bit 0) is set
to 0 after the STRT bit is set. If
INIT and STRT are set together,
RXON will not be set until after
the initialization block has been
read in.
RXON is read only. RXON is
cleared
S_RESET and setting the STOP
bit.
transmit function is enabled.
TXON is set if DTX (CSR15, bit 1)
is set to 0 after the STRT bit is
set. If INIT and STRT are set to-
gether, TXON will not be set until
after the initialization block has
been read in.
This bit will reset if the DXSUFLO
bit (CSR3, bit 6) is reset and there
is an underflow condition encoun-
tered.
TXON is read only. TXON is
cleared
S_RESET and setting the STOP
bit.
causes the Buffer Management
Unit to access the Transmit De-
scriptor Ring without waiting for
the poll-time counter to elapse. If
TXON is not enabled, TDMD bit
will be reset and no Transmit De-
scriptor Ring access will occur.
Interrupt Enable allows INTA to
Receive On indicates that the re-
Transmit On indicates that the
Transmit Demand, when set,
by
by
H_RESET
H_RESET
P R E L I M I N A R Y
Am79C976
or
or
2
1
0
STOP
STRT
INIT
TDMD is required to be set if the
TXDPOLL bit in CSR4 is set. Set-
ting TDMD while TXDPOLL = 0
merely hastens the Am79C976
controller’s next access to a
Transmit Descriptor Ring Entry.
Read/Write accessible. TDMD is
set by writing a 1. Writing a 0 has
no effect. TDMD will be cleared
by the Buffer Management Unit
when it fetches a Transmit De-
scriptor. TDMD is cleared by
H_RESET or S_RESET and set-
ting the STOP bit.
Read/Write accessible. STOP is
set by writing a 1, by H_RESET
or S_RESET. Writing a 0 has no
effect. STOP is cleared by setting
either STRT or INIT.
Read/Write accessible. STRT is
set by writing a 1. Writing a 0 has
no effect. STRT is cleared by
H_RESET, S_RESET, or by set-
ting the STOP bit.
Read/Write accessible. INIT is
set by writing a 1. Writing a 0 has
from all DMA activity. The chip re-
mains inactive until either STRT
or INIT are set. If STOP, STRT
and INIT are all set together,
STOP will override STRT and
INIT.
Am79C976 controller to send and
receive frames, and perform buff-
er management operations. Set-
ting STRT clears the STOP bit. If
STRT and INIT are set together,
the Am79C976 controller initial-
ization will be performed first.
Am79C976 controller to begin the
initialization
reads in the initialization block
from memory. Setting INIT clears
the STOP bit. If STRT and INIT
are set together, the Am79C976
controller initialization will be per-
formed first. INIT is not cleared
when the initialization sequence
has completed.
STOP assertion disables the chip
STRT
INIT
assertion
assertion
procedure
enables
8/01/00
enables
which
the