AM79C976 Advanced Micro Devices, AM79C976 Datasheet - Page 287
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AM79C976
Manufacturer Part Number
AM79C976
Description
PCnet-PRO 10/100 Mbps PCI Ethernet Controller
Manufacturer
Advanced Micro Devices
Datasheet
1.AM79C976.pdf
(309 pages)
- Current page: 287 of 309
- Download datasheet (3Mb)
Outline of LAPP Flow
This section gives a suggested outline for a driver that
utilizes the LAPP feature of the Am79C976 controller.
Note: The labels in the following text are used as ref-
e r e n c e s i n t h e t i m e l i n e d i a gr am t h a t fo l l ow s
(Figure A-1).
The driver should set up descriptors in groups of three,
with the OWN and STP bits of each set of three de-
scriptors to read as follows: 11b, 10b, 00b.
An option bit (LAPPEN) exists in CSR3, bit position 5;
the software should set this bit. When set, the LAPPEN
bit directs the Am79C976 controller to generate an IN-
TERRUPT when STP has been written to a receive de-
scriptor by the Am79C976 controller.
The Am79C976 controller polls the current receive de-
scriptor at some point in time before a message arrives.
The Am79C976 controller determines that this receive
buffer is OWNed by the Am79C976 controller and it
stores the descriptor information to be used when a
message does arrive.
N0
N1
C0
C1
S1
C2
C3
S1
8/01/00
Frame preamble appears on the wire, followed
by SFD and destination address.
The 64th byte of frame data arrives from the
wire. This causes the Am79C976 controller to
begin frame data DMA operations to the first
buffer.
When the 64th byte of the message arrives,
the Am79C976 controller performs a looka-
head operation to the next receive descriptor.
This descriptor should be owned by the
Am79C976 controller.
The Am79C976 controller intermittently re-
quests the bus to transfer frame data to the first
buffer as it arrives on the wire.
The driver remains idle.
When the Am79C976 controller has com-
pletely filled the first buffer, it writes status to
the first descriptor.
When the first descriptor for the frame has
been written, changing ownership from the
A m 7 9 C 9 7 6 c o n t r o l l e r t o t h e C P U, th e
Am79C976 controller will generate an SRP IN-
TERRUPT. (This interrupt appears as a RINT
interrupt in CSR0).
The SRP INTERRUPT causes the CPU to
switch tasks to allow the Am79C976 control-
ler’s driver to run.
P R E L I M I N A R Y
Am79C976
C4
Note: Even though the third buffer is not owned by the
Am79C976 controller, existing AMD Ethernet control-
lers will continue to perform data DMA into the buffer
space that the controller already owns (i.e., buffer num-
ber 2). The controller does not know if buffer space in
buffer number 2 will be sufficient or not for this frame,
but it has no way to tell except by trying to move the en-
tire message into that space. Only when the message
does not fit will it signal a buffer error condition--there is
no need to panic at this point that it discovers that it
does not yet own descriptor number 3.
S2
S3
C5
S4
S5
C6
During the CPU interrupt-generated task
switching, the Am79C976 controller is per-
forming a lookahead operation to the third de-
scr iptor. At this point in time, the third
descriptor is owned by the CPU.
route is to collect the header information from
the Am79C976 controller’s first buffer and
pass it to the application.
pointer to the driver. The driver will add an off-
set to the application data buffer pointer, since
the Am79C976 controller will be placing the
first portion of the message into the first and
second buffers. (the modified application data
buffer pointer will only be directly used by the
Am79C976 controller when it reaches the third
buffer.) The driver will place the modified data
buffer pointer into the final descriptor of the
group (#3) and will grant ownership of this de-
scriptor to the Am79C976 controller.
the Am79C976 controller will write frame data
to buffer number 2.
tents of the Am79C976 controller’s first buffer
to the beginning of the application space. This
copy will be to the exact (unmodified) buffer
pointer that was passed by the application.
into the beginning of the application data
buffer, the driver will begin to poll the owner-
ship bit of the second descriptor. The driver is
waiting for the Am79C976 controller to finish
filling the second buffer.
owned the third descriptor and knowing that
the current message has not ended (there is
more data in the FIFO), the Am79C976 con-
troller will make a last ditch lookahead to the
final (third) descriptor. This time the ownership
will be TRUE (i.e., the descriptor belongs to the
controller), because the driver wrote the appli-
The first task of the drivers interrupt service
The application will return an application buffer
Interleaved with S2, S3, and S4 driver activity,
The driver will next proceed to copy the con-
After copying all of the data from the first buffer
At this point, knowing that it had not previously
A-2
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