AM79C976 Advanced Micro Devices, AM79C976 Datasheet - Page 184

• Manufacturer Part Number: AM79C976
• Description: PCnet-PRO 10/100 Mbps PCI Ethernet Controller
• Manufacturer: Advanced Micro Devices

0
Bit
31-16
15-0
Bit
31-16
15-0
Bit
31-16
184
LADRF[31:16]
MIIPDTINTEMII PHY Detect Transition Inter-
Name
RES
LADRF[15:0]
Name
RES
Name
RES
rupt Enable. If MIIPDTINTE is set
to 1, the MIIPDTINT bit will be
able to set the INTR bit.
Read/Write
DTINTE is set to 0 by H_RESET
and is not affected by S_RESET
or setting the STOP bit.
zeros and read as undefined.
Logical
LADRF-[15:0]. The content of this
register is undefined until loaded
from the initialization block after
the INIT bit in CSR0 has been set
or a direct register write has been
performed on this register.
Read/Write accessible. These
bits are cleared by H_RESET but
are unaffected by S_RESET, or
STOP.
zeros and read as undefined.
Logical Address Filter, LADRF-
[31:16]. The content of this regis-
ter is undefined until loaded from
the initialization block after the
INIT bit in CSR0 has been set or
a direct register write has been
performed on this register.
Read/Write accessible. These
bits are cleared by H_RESET but
are unaffected by S_RESET, or
STOP.
zeros and read as undefined.
Reserved locations. Written as
Reserved locations. Written as
Reserved locations. Written as
Description
Description
Description
Address
accessible.
P R E L I M I N A R Y
Filter,
MIIP-
Am79C976
15-0 LADRF[47:32]Logical
Bit
31-16 RES
15-0
Note: Bits 15-0 in this register are programmable
through the EEPROM.
Bit
31-16 RES
15-0
LADRF[63:48]
Name
Name
PADR[15:0] Physical
Read/Write accessible. These
bits are cleared by H_RESET but
are unaffected by S_RESET, or
STOP.
Logical
LADRF[63:48]. The content of
this register is undefined until
loaded from the initialization
block after the INIT bit in CSR0
has been set or a direct register
write has been performed on this
register.
Read/Write accessible. These
bits are cleared by H_RESET but
are unaffected by S_RESET, or
STOP.
LADRF[47:32]. The content of
this register is undefined until
loaded from the initialization
block after the INIT bit in CSR0
has been set or a direct register
write has been performed on this
register.
zeros and read as undefined.
zeros and read as undefined.
PADR[15:0]. The contents of this
register
EEPROM after H_RESET or by
an EEPROM read command
(PREAD, BCR19, bit 14). If the
EEPROM is not present, the con-
tents of this register are unde-
fined.
from the initialization block after
the INIT bit in CSR0 has been set
Description
Reserved locations. Written as
Description
Reserved locations. Written as
This register can also be loaded
are
Address
Address
Address
loaded
Register,
8/01/00
Filter,
Filter,
from