AM79C976 Advanced Micro Devices, AM79C976 Datasheet - Page 144

• Manufacturer Part Number: AM79C976
• Description: PCnet-PRO 10/100 Mbps PCI Ethernet Controller
• Manufacturer: Advanced Micro Devices

Offset 074h
144
SWSTYLE
31-8
2-0
7-0
Bit
Bit
3
[7:0]
00h
01h
SWSTYLE
XPHYSP
APDW
Name
Name
RES
PCnet-ISA controller
LANCE/
Name
Style
RES
External PHY Speed. When set, this bit will force the external PHY into 100 Mbps mode when Auto-
Negotiation is not enabled.
XPHYSP is only valid when the internal Network Port Manager is scanning for a network port.
This bit is an alias of BCR32, bit 3.
MII Auto-Poll Dwell Time. APDW determines the dwell time between MII Management Frames
accesses when Auto-Poll is turned on.
The default value of this field is 100b.
This field is an alias of BCR32, bits 10:8.
Reserved locations. Written as zeros and read as undefined.
Software Style register. The value in this register determines the style of register and memory
resources that shall be used by the Am79C976 controller. The Software Style selection will affect
the interpretation of a few bits within the CSR space, the order of the descriptor entries, and the
width of the descriptors and initialization block entries.
All Am79C976 controller CSR bits and BCR bits and all descriptor, buffer, and initialization block
entries not cited in Table 50 are unaffected by the Software Style selection and are, therefore,
always fully functional as specified in the CSR and BCR sections.
Table 49.
110-111
SSIZE32
P R E L I M I N A R Y
Table 50. Software Styles
APDW
000
001
010
011
100
101
0
1
CTRL3: Control3 Register
Am79C976
Continuous (26ms @ 2.5 MHz)
Every 64 MDC cycles (51ms @ 2.5 MHz)
Every 128 MDC cycles (103ms @ 2.5 MHz)
Every 256 MDC cycles (206 ms @ 2.5 MHz)
Every 512 MDC cycles (410 ms @ 2.5 MHz)
Every 1024 MDC cycles (819 ms @ 2.5 MHz)
Reserved
16-bit software structures,
non-burst or burst access
RES
Initialization Block Entries
All bits in this register are set to their default values by
H_RESET. All bits are also set to their default values
before EEPROM data are loaded or after an EEPROM
read failure.
The default value for all bits is 0.
Description
Description
Auto-PollÉ Dwell Time
16-bit software structures, non-
burst access only
RES
Descriptor Ring Entries
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