AM79C976 Advanced Micro Devices, AM79C976 Datasheet - Page 34

• Manufacturer Part Number: AM79C976
• Description: PCnet-PRO 10/100 Mbps PCI Ethernet Controller
• Manufacturer: Advanced Micro Devices

The Am79C976 controller will not assert DEVSEL if it
detects an address match, but the PCI command is not
of the correct type. In memory mapped I/O mode, the
Am79C976 controller aliases all accesses to the I/O re-
sources of the command types Memory Read Multiple
and Memory Read Line to the basic Memory Read
command. All accesses of the type Memory Write and
Invalidate are aliased to the basic Memory Write com-
mand. Eight-bit, 16-bit, and 32-bit transactions are sup-
ported. The Am79C976 controller decodes all 32
address lines to determine which I/O resource is ac-
cessed.
The number of wait states added to slave transactions
varies. Typical values are shown in the table below:
access is a memory cycle. DEVSEL is asserted two
clock cycles after the host has asserted FRAME. See
Figure 11 and Figure 22.
34
Memory-mapped
transactions
I/O-mapped transactions
Slave Transactions
DEVSEL
FRAME
IDSEL
TRDY
STOP
C/BE
IRDY
CLK
PAR
AD
1
ADDR
1010
2
PAR
3
4
Read
BE
Transaction Type
9
9
5
DATA
PAR
6
6
P R E L I M I N A R Y
Write
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3
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Am79C976
For compatibility with older members of the PCnet family
of controllers, the 32 lowest addresses of the I/O or
memory space claimed by the Am79C976 device sup-
port indirect addressing of internal registers. The
Am79C976 controller does not support burst transfers
for access to these locations. When the host keeps
FRAME asserted for a second data phase in this ad-
dress range, the Am79C976 controller will disconnect
the transfer. However, the controller does support burst
accesses to locations at offsets 32 and above.
Because of the side effects of reading the Reset Reg-
ister at offset 14h or 18h (depending on the state of
DWIO (CMD2, bit 28)), locations at offsets less than
20h cannot be prefetched.
The Am79C976 controller supports fast back-to-back
transactions to different targets. This is indicated by the
Fast Back-To-Back Capable bit (PCI Status register, bit
7), which is hardwired to 1. The Am79C976 controller
is capable of detecting an I/O or a memory-mapped
I/O cycle even when its address phase immediately fol-
lows the data phase of a transaction to a different target,
without any idle state in-between. There will be no con-
tention on the DEVSEL, TRDY, and STOP signals, since
the Am79C976 controller asserts DEVSEL on the sec-
ond clock after FRAME is asserted (medium timing).
See Figure 33 and Figure 44.
DEVSEL
FRAME
IDSEL
STOP
TRDY
C/BE
IRDY
CLK
PAR
AD
1
ADDR
1011
2
PAR
3
4
DATA
BE
5
PAR
6
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