AM79C976 Advanced Micro Devices, AM79C976 Datasheet - Page 153

• Manufacturer Part Number: AM79C976
• Description: PCnet-PRO 10/100 Mbps PCI Ethernet Controller
• Manufacturer: Advanced Micro Devices

INT0: Interrupt0
Offset 038h
INT0 identifies the source or sources of an interrupt.
With the exception of INTR, all bits in this register are
“write 1 to clear” so that the CPU can clear the interrupt
condition by reading the register and then writing back
8/01/00
31-28
Bit
31
27
26
25
24
23
22
21
20
19
18
17
MIIPDTINT
MCCIINT
MCCINT
APINT5
APINT4
APINT3
APINT2
APINT1
APINT0
LCINT
Name
INTR
RES
RES
Interrupt Summary. This bit indicates that one or more of the other interrupt bits in this register are
set and the associated enable bit or bits in INTEN0 are also set. If INTREN in CMD0 is set to 1 and
INTR is set, INTA will be active. When INTR is set by SINT, INTA will be active independent of the
state of INEA.
INTR is read only. INTR is cleared by clearing all of the active individual interrupt bits that have not
been masked out.
Reserved locations. Written as zeros and read as undefined.
Link Change Interrupt. This bit is set when the Port Manager detects a change in the link status of
the external PHY.
Auto-Poll Interrupt from Register 5. This bit is set when the Auto-Poll State Machine has detected
a change in the external PHY register whose address is stored in Auto-Poll Register 5.
Auto-Poll Interrupt from Register 4. This bit is set when the Auto-Poll State Machine has detected
a change in the external PHY register whose address is stored in Auto-Poll Register 4.
Auto-Poll Interrupt from Register 3. This bit is set when the Auto-Poll State Machine has detected
a change in the external PHY register whose address is stored in Auto-Poll Register 3.
Reserved locations. Written as zeros and read as undefined.
Auto-Poll Interrupt from Register 2. This bit is set when the Auto-Poll State Machine has detected
a change in the external PHY register whose address is stored in Auto-Poll Register 2.
Auto-Poll Interrupt from Register 1. This bit is set when the Auto-Poll State Machine has detected
a change in the external PHY register whose address is stored in Auto-Poll Register 1.
Auto-Poll Interrupt from Register 0. This bit is set when the Auto-Poll State Machine has detected
a change in the external PHY register whose address is stored in Auto-Poll Register 0.
MII PHY Detect Transition Interrupt. The MII PHY Detect Transition Interrupt is set by the
Am79C976 controller whenever the MIIPD bit in STAT0 transitions from 0 to 1 or vice versa.
This bit is an alias of CSR7, bit 1.
MII Management Command Complete Internal Interrupt. The MII Management Command
Complete Interrupt is set by the Am79C976 controller when a read or write operation on the MII
management port is complete from an internal operation. Examples of internal operations are Auto-
Poll or Network Port Manager generated MII management frames.
This bit is an alias of CSR7, bit 3.
MII Management Command Complete Interrupt. The MII Management Command Complete
Interrupt is set by the Am79C976 controller when a read or write operation to the MII Data Port
(PHY Access Register) is complete.
This bit is an alias of CSR7, bit 5.
Table 59.
P R E L I M I N A R Y
INT0: Interrupt0 Register
Am79C976
the same data that it read. Writing a 0 to a bit in this reg-
ister has no effect.
All bits in this register are cleared to 0 by H_RESET. In
addition, TINT, TXDNINT, TXSTRTINT, and RINT are
cleared when the RUN bit in CMD0 is cleared.
Description
153