AM79C976 Advanced Micro Devices, AM79C976 Datasheet - Page 195

• Manufacturer Part Number: AM79C976
• Description: PCnet-PRO 10/100 Mbps PCI Ethernet Controller
• Manufacturer: Advanced Micro Devices

3
2
1
0
Bit
31-0
Bit
31-16
8/01/00
RWU_DRIVER RWU Driver Type. If this bit is set
RWU_GATE RWU Gate Control. If this bit is
RWU_POL RWU Pin Polarity. If RWU_POL
RST_POL
Name
RES
Name
RES
by S_RESET or setting the STOP
bit.
to 1, RWU is a totem pole driver;
otherwise RWU is an open drain
output.
by H_RESET and is not affected
by S_RESET or setting the STOP
bit.
set, RWU is forced to the high Im-
pedance State when PG is LOW,
regardless of the state of the
MPMAT and LCDET bits.
by H_RESET and is not affected
by S_RESET or setting the STOP
bit.
is set to 1, the RWU pin is normal-
ly HIGH and asserts LOW; other-
wise, RWU is normally LOW and
asserts HIGH.
by H_RESET and is not affected
by S_RESET or setting the STOP
bit.
PHY_POL is set to 1, the
PHY_RST pin is active LOW; oth-
erwise,
HIGH.
by H_RESET and is not affected
by S_RESET or setting the STOP
bit.
zeros and read as undefined.
zeros and read as undefined.
Read/Write accessible. Cleared
Read/Write accessible. Cleared
Read/Write accessible. Cleared
PHY_RST Pin Polarity. If the
Read/Write accessible. Cleared
Reserved locations. Written as
Reserved locations. Written as
Description
Description
PHY_RST
P R E L I M I N A R Y
is
active
Am79C976
15-2
0
Bit
31-0
This register is used to place the Am79C976 controller
into various test modes. The Runt Packet Accept is the
only user accessible test mode. All other test modes are
for AMD internal use only.
Bit
31-16 RES
15-4
3
RES
RCVALGN Receive Packet Align. When set,
Name
RES
Name
RES
RPA
Read/Write
RCVALGN
H_RESET or S_RESET and is
not affected by STOP.
The minimum packet size that
can be received is 12 bytes.
zeros and read as undefined.
this bit forces the data field of ISO
8802-3 (IEEE/ANSI 802.3) pack-
ets to align to 0 MOD 4 address
boundaries (i.e., DWord aligned
addresses). It is important to note
that this feature will only function
correctly if all receive buffer
boundaries are DWord aligned
and all receive buffers have 0
MOD 4 lengths. In order to ac-
complish the data alignment, the
Am79C976 controller simply in-
serts two bytes of random data at
the beginning of the receive
packet (i.e., before the ISO 8802-
3 (IEEE/ANSI 802.3) destination
address field). The MCNT field
reported to the receive descriptor
will not include the extra two
bytes.
zeros and read as undefined.
zeros and read as undefined.
zeros and read as undefined.
es the Am79C976 controller to
accept runt packets (packets
shorter than 64 bytes).
Reserved locations. Written as
Description
Reserved locations. Written as
Description
Reserved locations. Written as
Reserved locations. Written as
Runt Packet Accept. This bit forc-
is
cleared
accessible.
195
by