AM79C976 Advanced Micro Devices, AM79C976 Datasheet - Page 229

• Manufacturer Part Number: AM79C976
• Description: PCnet-PRO 10/100 Mbps PCI Ethernet Controller
• Manufacturer: Advanced Micro Devices

The following tables describe the bits of the receive
descriptors in more detail.
8/01/00
Offset
0
2
4
6
15-12
15-0
15-0
11-0
7-0
Bit
15
14
13
12
11
10
9
8
RBADR[23:16]
RBADR
ZEROS
FRAM
MCNT
Name
OFLO
BCNT
OWN
ERR
CRC
ENP
STP
Receive Buffer Address. This field contains the address of the receive buffer that is
associated with this descriptor.
This bit indicates whether the descriptor entry is owned by the host (OWN = 0) or by
the Am79C976 controller (OWN = 1). The host sets the OWN bit after it has emptied
the buffer pointed to by the descriptor entry. The Am79C976 controller clears the
OWN bit after filling the buffer that the description points to. Both the Am79C976
controller and the host must not alter a descriptor entry after it has relinquished
ownership.
Error Summary.
Am79C976 controller and cleared by the host.
Framing error indicates that the incoming frame contains a non-integer multiple of
eight bits and there was an FCS error. If there was no FCS error on the incoming
frame, then FRAM will not be set even if there was a non- integer multiple of eight bits
in the frame. FRAM is not valid in internal loopback mode. FRAM is valid only when
ENP is set and OFLO is not. FRAM is set by the Am79C976 controller and cleared by
the host.
Overflow error indicates that the receiver has lost all or part of the incoming frame,
due to an inability to move data from the receive FIFO into a memory buffer before the
internal FIFO overflowed. OFLO is set by the Am79C976 controller and cleared by the
host.
CRC indicates that the receiver has detected a CRC (FCS) error on the incoming
frame. CRC is valid only when ENP is set and OFLO is not. CRC is set by the
Am79C976 controller and cleared by the host. CRC will also be set when Am79C976
receives an RX_ER indication from the external PHY through the MII.
Reserved.
Start of Packet indicates that this is the first buffer used by the Am79C976 controller
for this frame. If STP and ENP are both set to 1, the frame fits into a single buffer.
Otherwise, the frame is spread over more than one buffer. When LAPPEN (CSR3, bit
5) is cleared to 0, STP is set by the Am79C976 controller and cleared by the host.
When LAPPEN is set to 1, STP must be set by the host.
End of Packet indicates that this is the last buffer used by the Am79C976 controller for
this frame. It is used for data chaining buffers. If both STP and ENP are set, the frame
fits into one buffer and there is no data chaining. ENP is set by the Am79C976
controller and cleared by the host.
Receive Buffer Address (high order bits)
Buffer Byte Count is the length of the buffer pointed to by this descriptor, expressed
as the two’s complement of the length of the buffer. This field is written by the host and
unchanged by the Am79C976 controller.
This field is reserved. Am79C976 controller will write zeros to these locations.
Message Byte Count is the number of bytes of the received message written to the
receive buffer. This is the actual frame length (including FCS) unless stripping is
enabled and the length field is < 46 bytes. In this case, MCNT is 14 + length_field.
MCNT can take values in the range 15 to 59 and values greater than or equal to 64.
MCNT is expressed as an unsigned binary integer. MCNT is valid only when ERR is
clear and ENP is set. MCNT is written by the Am79C976 controller and cleared by the
host.
P R E L I M I N A R Y
Am79C976
ERR is the OR of FRAM, OFLO, and CRC. ERR is set by the
Description
229