AM79C976 Advanced Micro Devices, AM79C976 Datasheet - Page 216

• Manufacturer Part Number: AM79C976
• Description: PCnet-PRO 10/100 Mbps PCI Ethernet Controller
• Manufacturer: Advanced Micro Devices

Bit
31-16
15
14
13-6
5-3
2-0
216
Maximum SRAM_BND Address
Minimum SRAM_BND
Table 93. SRAM_BND Programming
SRAM Addresses
Name
RES
PTR TST
RES
EBCS
CLK_FAC
LOLATRX Obsolete function. Writing has no
Address
Values larger than IFFCh will
cause incorrect behavior.
Note: The minimum allowed
number of pages is four and the
maximum is SRAM_SIZE-4. The
Am79C976 controller will not op-
erate correctly with less than four
pages of memory per queue. See
Table 93 for SRAM_BND pro-
gramming details.
CAUTION:
SRAM_BND and SRAM_SIZE to
the same value will cause data
corruption.
Read/Write
SRAM_BND is set to 00000000b
during H_RESET and is unaffect-
ed by S_RESET or STOP.
zeros and read as undefined.
facturing tests. Written as zero
and read as undefined.
Note: Use of this bit will cause
data corruption and erroneous
operation.
Read/Write
PTR_TST
H_RESET and is unaffected by
S_RESET and the STOP bit.
effect. Read as undefined.
zeros and read as undefined.
effect. Read as undefined.
effect. Read as undefined.
Reserved locations. Written as
Reserved. Reserved for manu-
Reserved locations. Written as
Obsolete function. Writing has no
Obsolete function. Writing has no
Description
is
SRAM_BND 11:0]
SRAM_SIZE - 4
set
Programming
004h
P R E L I M I N A R Y
accessible.
accessible.
to
0
Am79C976
by
Bit
31-16 RES
15-0
Bit
31-16 RES
15
14
EPADDRL
FLASH
LAAINC
Name
Name
Reserved locations. Written as
zeros and read as undefined.
Expansion Port Address Lower.
This address is used to provide
addresses for the Flash port ac-
cesses.
Flash accesses are started when
a read or write is performed on
BCR30. During Flash accesses
all bits in EPADDR are valid.
Read accessible always; write
accessible only when STOP is
set
(BCR25, bits 7-0) is 0. EPADDRL
is undefined after H_RESET and
is unaffected by S_RESET or
STOP.
Reserved locations. Written as
zeros and read as undefined.
Obsolete function. Read only. Al-
ways returns logic 1.
Lower Address Auto Increment.
When the LAAINC bit is set to 1,
the Expansion Port Lower Ad-
dress will automatically increment
by one after a read or write ac-
cess to EBDATA (BCR30). When
EBADDRL reaches FFFFh and
LAAINC is set to 1, the Expansion
Port Lower Address (EPADDRL)
will roll over to 0000h. When the
LAAINC bit is set to 0, the Expan-
sion Port Lower Address will not
be affected in any way after an
access to EBDATA (BCR30) and
must be programmed.
Read accessible always; write
accessible only when the STOP
bit is set. LAINC is 0 after
H_RESET and is unaffected by
S_RESET or the STOP bit.
Description
Description
or
when
SRAM_SIZE
8/01/00