AM79C976 Advanced Micro Devices, AM79C976 Datasheet - Page 143

• Manufacturer Part Number: AM79C976
• Description: PCnet-PRO 10/100 Mbps PCI Ethernet Controller
• Manufacturer: Advanced Micro Devices

CTRL2: Control2 Register
Offset 070h
This register contains several miscellaneous control
bits. Each byte of this register controls a single func-
tion. It is not necessary to do a read-modify-write oper-
ation to change a function’s settings if only a single byte
of the register is written.
8/01/00
31-19
18-16
15-10
9-8
Bit
7
6
5
4
XPHYRST
XPHYANE
XPHYFD
FMDC
Name
RES
RES
RES
FS
Reserved locations. Written as zeros and read as undefined.
Force Speed. This three-bit field sets the MAC’s internal speed indicator according to the table
below. The speed indication is used only for LEDs.
Reserved locations. Written as zeros and read as undefined.
Fast Management Data Clock. When FMDC is set to 2h the MII Management Data Clock will run
at 10 MHz max. The Management Data Clock will no longer be IEEE 802.3u-compliant and setting
this bit should be used with care. The accompanying external PHY must also be able to accept
management frames at the new clock rate. When FMDC is set to 1h, the MII Management Data
Clock will run at 5 MHz max. The Management Data Clock will no longer be IEEE 802.3u-compliant
and setting this bit should be used with care. The accompanying external PHY must also be able
to accept management frames at the new clock rate. When FMDC is set to 0h, the MII Management
Data Clock will run at 2.5 MHz max and will be fully compliant to IEEE 802.3u standards.
This field is an alias of BCR32, bits13:12
Reserved location. Written as zero and read as undefined.
External PHY Reset. When XPHYRST is set, the Am79C976 controller after an H_RESET or
S_RESET will issue an MII management frame that will reset the external PHY. This bit is needed
when there is no way to guarantee the state of the external PHY. This bit must be reprogrammed
after every H_RESET.
XPHYRST is only valid when the internal Network Port Manager is scanning for a network port.
This bit is an alias of BCR32, bit 6.
External PHY Auto-Negotiation Enable. This bit will force the external PHY into enabling Auto-
Negotiation. When set to 0 the Am79C976 controller will send an MII management frame disabling
Auto-Negotiation.
XPHYANE is only valid when the internal Network Port Manager is scanning for a network port.
This bit is an alias of BCR32, bit 5.
External PHY Full Duplex. When set, this bit will force the external PHY into full duplex when Auto-
Negotiation is not enabled.
XPHYFD is only valid when the internal Network Port Manager is scanning for a network port.
This bit is an alias of BCR32, bit 4.
Table 48.
P R E L I M I N A R Y
CTRL2: Control2 Register
FS[2:0]
Am79C976
1XX
000
001
010
011
All bits in this register are set to their default values by
H_RESET. All bits are also set to their default values
before EEPROM data are loaded or after an EEPROM
read failure.
The default value for all bits except for bits 2:0 (APDW)
is 0. The default value for the APDW field is 100b.
Speed determined by PHY
Description
Reserved
Reserved
100 Mb/s
10 Mb/s
Speed
143