AM79C976 Advanced Micro Devices, AM79C976 Datasheet - Page 81

• Manufacturer Part Number: AM79C976
• Description: PCnet-PRO 10/100 Mbps PCI Ethernet Controller
• Manufacturer: Advanced Micro Devices

The Am79C976 controller provides bits in each of the
LED Status registers (BCR4, BCR5, BCR6, BCR7) to
display the Full-Duplex Link Status. If the FDLSE bit (bit
8) is set, a value of 1 will be sent to the associated LED-
OUT bit when in Full-Duplex.
Media Independent Interface
The Am79C976 controller fully suppor ts the MII
according to the IEEE 802.3 standard. This Reconcili-
ation Sublayer interface allows a variety of PHYs
( 1 0 0 B A S E - T X , 1 0 0 B A S E - F X , 1 0 0 B A S E - T 4 ,
100BASE-T2, 10BASE-T, etc.) to be attached to the
Am79C976 MAC engine without future upgrade prob-
lems. The MII interface is a 4-bit (nibble) wide data path
interface that runs at 25 MHz for 100-Mbps networks or
2.5 MHz for 10-Mbps networks. The interface consists
of two independent data paths, receive (RXD(3:0)) and
transmit (TXD(3:0)), control signals for each data path
(RX_ER, RX_DV, TX_EN), network status signals
(COL, CRS), clocks (RX_CLK, TX_CLK) for each data
path, and a two-wire management interface (MDC and
MDIO). See Figure 3333.
The transmit and receive paths in the Am79C976 con-
troller's MAC are independent. The TX_CLK and
RX_CLK need not run at the same frequency. TX_CLK
can slow down or stop without affecting receive and
8/01/00
— Transmission is not deferred while receive is
— The IPG counter which governs transmit deferral
active.
during the IPG between back-to-back transmits
is started when transmit activity for the first
packet ends, instead of when transmit and car-
rier activity ends.
P R E L I M I N A R Y
Am79C976
vice versa. It is only necessary to respect the minimum
clock high and low time specifications when switching
TX_CLK or RX_CLK. This facilitates operation with
PHYs that use MII signaling but do not adhere to 802.3
MII specifications.
The MII transmit clock is generated by the external
PHY and is sent to the Am79C976 controller on the
TX_CLK input pin. The clock can run at 25 MHz or 2.5
MHz, depending on the speed of the network to which
the external PHY is attached. The data is a nibble-wide
(4 bits) data path, TXD(3:0), from the Am79C976 con-
troller to the external PHY and is synchronous with the
rising edge of TX_CLK. The transmit process starts
when the Am79C976 controller asserts TX_EN, which
indicates to the external PHY that the data on TXD(3:0)
is valid.
IEEE Std 802.3 provides a mechanism for signalling
unrecoverable errors through the MII to the external
PHY with the TX_ER output pin. The external PHY will
respond to this error by generating a TX coding error on
the current transmitted frame. The Am79C976 control-
ler does not use this method of signaling errors on the
transmit side. Instead if the Am79C976 controller de-
tects a transmit error, it will invert the FCS to generate
an invalid FCS. Since the Am79C976 controller does
not implement the TX_ER function, the TX_ER pin on
the external PHY device should be connected to VSS.
The MII receive clock is also generated by the external
PHY and is sent to the Am79C976 controller on the
RX_CLK input pin. The clock will be the same fre-
quency as the TX_CLK but will be out of phase and can
run at 25 MHz or 2.5 MHz, depending on the speed of
the network to which the external PHY is attached.
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