AM79C976 Advanced Micro Devices, AM79C976 Datasheet - Page 163

• Manufacturer Part Number: AM79C976
• Description: PCnet-PRO 10/100 Mbps PCI Ethernet Controller
• Manufacturer: Advanced Micro Devices

Offset 0D0h
This register gives the host CPU indirect access to the
MII Management Bus (MDC/MDIO). Through this reg-
ister the host CPU can read or write any external PHY
8/01/00
PHY Access Register
25-21
20-16
15-0
Bit
31
30
29
28
27
26
PHY_BLK_RD_CMD
PHY_NBLK_RD_CM
PHY_CMD_DONE
PHY_REG_ADDR
PHY_PRE_SUP
PHY_WR_CMD
PHY_ADDR
PHY_DATA
Name
RES
D
PHY Command Complete. This read-only bit is set to 0 after a write access to this register and
remains 0 until the end of the MII Management Frame that is generated by the write access.
When the value of this bit is 1, the PHY_DATA field contains valid data.
PHY Write Command. When this bit is set, an MII Management Frame will be sent to write the
contents of the PHY_DATA field to the external PHY register addressed by the PHY_ADDR and
PHY_REG_ADDR fields. This bit must not be set at the same time that the
PHY_BLK_RD_CMD bit or the PHY_NBLK_RD_CMD bit is set.
PHY Blocking Read Command. When the bit is set, an MII Management Frame will be sent to
read the contents of the PHY_DATA field to the external PHY register addressed by the
PHY_ADDR and PHY_REG_ADDR fields. After this bit is set, the next attempt to read this
register will cause PCI bus retries to occur until the PHY_DATA field has been updated with
data read from the selected PHY register.
This bit must not be set at the same time that the PHY_WR_CMD bit or the
PHY_NBLK_RD_CMD bit is set.
PHY Non-Blocking Read Command. When the bit is set, an MII Management Frame will be
sent to read the contents of the PHY_DATA field to the external PHY register addressed by the
PHY_ADDR and PHY_REG_ADDR fields. After this bit is set, the host CPU can read this
register again and again until the PHY_CMD_DONE bit returns the value 1, indicating that the
PHY_DATA field contains valid data read from the selected PHY register. Alternatively, the host
CPU can wait for the MCCINT interrupt (INT0, bit 17).
This bit must not be set at the same time that the PHY_WR_CMD bit or the
PHY_BLK_RD_CMD bit is set.
Preamble Suppression. If this bit is set, the MII Management Frame will be sent without a
preamble. Before setting this bit the host CPU must make sure that the external PHY
addressed by the PHY_ADDR field is capable of accepting MII Management Frames without
preambles.
Reserved location. Written as zero and read as undefined.
PHY Data. Data written to or read from the external PHY register specified by PHY_ADDR and
PHY_REG_ADDR.
PHY Address. The address of the external PHY device to be accessed.
PHY Register Address. The address of the register in the external PHY device to be accessed.
Table 69.
P R E L I M I N A R Y
PHY_ACCESS: PHY Access Register
Am79C976
register that is accessible through the MII Management
Bus.
All bits in this register are cleared to 0 when the RST
pin is asserted. This register is not affected by the serial
EEPROM read operation or by a serial EEPROM read
error.
Description
163