AM79C976 Advanced Micro Devices, AM79C976 Datasheet - Page 129

• Manufacturer Part Number: AM79C976
• Description: PCnet-PRO 10/100 Mbps PCI Ethernet Controller
• Manufacturer: Advanced Micro Devices

BADX: Transmit Ring Base Address Register
Offset 100h
This 64-bit register allows the Transmit Descriptor Ring
to be located anywhere in a 64-bit address space. For
systems with a 32-bit or smaller address space, it is
only necessary to program the lower 32 bits of this reg-
Offset 0F0h
Offset 18Ah
8/01/00
31-28
27-12
63-0
11-1
15-0
Bit
Bit
Bit
0
CHPOLL TIME
MANFID
PARTID
Name
BADX
Name
Name
ONE
VER
Version. This 4-bit pattern is silicon-revision dependent.
Part number. The 16-bit code for the Am79C976 controller is 0010 0110 0010 1000b (2628h).
This register is exactly the same as the Device ID register in the JTAG description. However, this
part number is different from that stored in the Device ID register in the PCI configuration space.
Manufacturer ID. The 11-bit manufacturer code for AMD is 00000000001b. This code is per the
JEDEC Publication 106-A.
Note that this code is not the same as the Vendor ID in the PCI configuration space.
Always logic 1.
Chain Polling Interval. This register contains the time that the Am79C976 controller will wait
between successive polling operations when the Buffer Management Unit is in the middle of a
buffer chaining operation. The CHPOLLTIME value is expressed as the two’s complement of the
desired interval, where each bit of CHPOLLTIME approximately represents 3 ERCLK periods.
CHPOLLTIME[3:0] are ignored. (CHPOLLTIME[16] is implied to be a 1, so CHPOLLTIME[15] is
significant and does not represent the sign of the two’s complement CHPOLLTIME value.)
The default value of this register is 0000h. This corresponds to a polling interval of 65,536 clock
periods (2.185 ms when ERCLK = 90 MHz).
Setting the INIT bit starts an initialization process that sets CHPOLLTIME to its default value. If the
user wants to program a value for CHPOLLTIME other than the default, then he must change the
value after the initialization sequence has completed.
This register is an alias for CSR49.
Base Address of Transmit Descriptor Ring. In systems with a 32-bit or smaller address space, it is
only necessary to program the 32 low-order bits of this register.
The low-order 32 bits of this register are an alias of CSR30 and CSR31.
Table 41.
Table 39.
Table 40. CHIPID: Chip ID Register
CHPOLLTIME: Chain Polling Interval Register
P R E L I M I N A R Y
Transmit Ring Base Address Register
Am79C976
ister (by writing to offset 100h). The upper 32 bits will
remain at the default value of 0.
The contents of this register are set to the default value
0 when the RST pin is asserted. This register is not af-
fected by the serial EEPROM read operation or by a se-
rial EEPROM read error.
This read-only register is an alias of CSR88.
The contents of this register are cleared to 0 when the
RST pin is asserted, before the serial EEPROM is
read, and after a serial EEPROM read error.
Description
Description
Description
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