AM79C976 Advanced Micro Devices, AM79C976 Datasheet - Page 148

• Manufacturer Part Number: AM79C976
• Description: PCnet-PRO 10/100 Mbps PCI Ethernet Controller
• Manufacturer: Advanced Micro Devices

148
12-5
Bit
15
14
13
4
3
PVALID
PREAD
EEDET
Name
RES
EEN
RES
EEPROM Valid status bit. PVALID is read only; write operations have no effect. A value of 1 in this
bit indicates that a PREAD operation has occurred, and that (1) there is an EEPROM connected to
the Am79C976 controller interface pins and (2) the contents read from the EEPROM have passed
the CRC verification operation.
A value of 0 in this bit indicates a failure in reading the EEPROM. The CRC for the EEPROM is
incorrect or no EEPROM is connected to the interface pins.
PVALID is set to 0 during H_RESET. However, following the H_RESET operation, an automatic
read of the EEPROM will be performed. Just as is true for the normal PREAD command, at the end
of this automatic read operation, the PVALID bit may be set to 1. Therefore, H_RESET will set the
PVALID bit to 0 at first, but the automatic EEPROM read operation may later set PVALID to a 1.
If PVALID becomes 0 following an EEPROM read operation (either automatically generated after
H_RESET, or requested through PREAD), then all EEPROM-programmable registers will be reset
to their default values. The content of the Address PROM locations, however, will not be cleared.
If no EEPROM is present at the EESK, EEDI, and EEDO pins, then all attempted PREAD
commands will terminate early and PVALID will not be set. This applies to the automatic read of
the EEPROM after H_RESET, as well as to host-initiated PREAD commands.
EEPROM Read command bit. When this bit is set to a 1 by the host, the PVALID bit (bit 15) will
immediately be reset to a 0, and then the Am79C976 controller will perform a read operation from
the external serial EEPROM. The EEPROM data that is fetched during the read will be stored in
the appropriate internal registers on board the Am79C976 controller. Upon completion of the
EEPROM read operation, the Am79C976 controller will assert the PVALID bit.
At the end of the read operation, the PREAD bit will automatically be reset to a 0 by the Am79C976
controller and PVALID will be set, provided that an EEPROM existed on the interface pins and that
the CRC for the EEPROM was correct.
Note that when PREAD is set to a 1, then the Am79C976 controller will no longer respond to any
accesses directed toward it until the PREAD operation has completed successfully. The
Am79C976 controller will terminate these accesses with the assertion of DEVSEL and STOP while
TRDY is not asserted, signaling to the initiator to disconnect and retry the access at a later time.
If a PREAD command is given to the Am79C976 controller but no EEPROM is attached to the
interface pins, the PREAD bit will be cleared to a 0, and the PVALID bit will remain reset with a
value of 0. This applies to the automatic read of the EEPROM after H_RESET as well as to host
initiated PREAD commands. All EEPROM programmable registers will be set to their default values
by such an aborted PREAD operation.
At the end of the read operation, if bit 15 of the PMC Alias register is zero or the VAUX_SENSE pin
is low, the PME_STATUS and PME_EN bits of the PMCSR register will be reset.
EEPROM Detect. This bit indicates whether or not an EEPROM was detected by the ERPROM
read operation. If this bit is a 1, it indicates that an EEPROM was detected. If this bit is a 0, it
indicates that an EEPROM was not detected.
EEDET is read only; write operations have no effect. The value of this bit is determined at the end
of the H_RESET operation.
Reserved locations. Written as zeros and read as undefined.
EEPROM Port Enable. When this bit is set to a 1, it causes the values of ECS, ESK, and EDI to be
driven onto the EECS, EESK, and EEDI pins, respectively. If EEN = 0 and no EEPROM read
function is currently active, then EECS will be driven LOW. When EEN = 0 and no EEPROM read
function is currently active, EESK and EEDI pins will be driven by the LED1 and LED0 functions,
respectively. See Table 54.
Reserved location. Written as 0; read as undefined.
Table 53. EEPROM_ACC: EEPROM Access Register
P R E L I M I N A R Y
Am79C976
Description
8/01/00