AM79C976 Advanced Micro Devices, AM79C976 Datasheet - Page 71

• Manufacturer Part Number: AM79C976
• Description: PCnet-PRO 10/100 Mbps PCI Ethernet Controller
• Manufacturer: Advanced Micro Devices

If REX_UFLO (CMD3, bit 7) is set, the transmitter will
not flush the frame data from the transmit FIFO after a
transmit FIFO underflow error occurs. Instead, it will
wait until the entire frame has been copied into the
transmit FIFO, and then it will restart the transmission
process.
The XmtLossCarrier counter is incremented if transmit
is attempted when the LINK_STAT bit in the STAT0 reg-
ister is 0.
A late collision will be detected when the device is op-
erating in half-duplex mode and a collision condition
occurs after one slot time (512 bit times) after the trans-
mit process was initiated (first bit of preamble com-
menced). When it detects a late collision, the
Am79C976 controller will increment the XmtLateColli-
sion counter. If RTRY_LCOL (CMD3, bit 16) is cleared
to 0, the controller will abandon the transmit process for
that frame, and process the next transmit frame in the
ring. If the RTRY_LCOL bit is set to 1, transmission at-
tempts that incur late collisions will be retried up to a
maximum of 16 attempts.
An underflow error occurs when the transmitter runs
out of data from the transmit FIFO in the middle of a
transmission. When this happens, an inverted FCS is
appended to the frame so that the intended receiver will
ignore the frame, and the XmtUnderrunPkts counter is
incremented. If REX_UFLO (CMD3, bit 17) is set to 1,
the transmitter will then wait until the entire frame has
been loaded into the transmit FIFO, and then it will re-
star t the transmission of the same frame. If the
REX_UFLO is cleared to 0, the transmitter will not at-
tempt to retransmit the aborted frame.
Receive Operation
The receive operation and features of the Am79C976
controller are controlled by programmable options. The
Am79C976 controller uses a large receive FIFO to pro-
vide frame buffering for increased system latency, au-
tomatic flushing of collision fragments (runt packets),
automatic receive pad stripping, and a variety of ad-
dress match options.
Automatic pad field stripping is enabled by setting the
ASTRP_RCV bit in CSR4. This can provide flexibility in
the reception of messages using the IEEE 802.3 frame
format.
The device can be programmed to accept all receive
frames regardless of destination address by setting the
PROM bit in CSR15. Acceptance of unicast and broad-
cast frames can be individually turned off by setting the
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P R E L I M I N A R Y
Am79C976
DRCVPA or DRCVBC bits in CSR15. The Physical Ad-
dress register (CSR12 to CSR14) stores the address
that the Am79C976 controller compares to the destina-
tion address of the incoming frame for a unicast ad-
dress match. The Logical Address Filter register
(CSR8 to CSR11) serves as a hash filter for multicast
address match.
The point at which the controller will start to transfer
data from the receive FIFO to buffer memory is con-
trolled by the RCVFW bits in CSR80. The default es-
tablished during H_RESET is 01b, which sets the
watermark flag at 64 bytes filled.
For test purposes, the Am79C976 controller can be
programmed to accept runt packets of 12 bytes or
larger by setting RPA in CSR124.
The Am79C976 controller supports three types of ad-
dress matching: unicast, multicast, and broadcast. The
normal address matching procedure can be modified
by programming three bits in CSR15, the mode register
(PROM, DRCVPA, and DRCVBC).
If the first bit received after the SFD (the least signifi-
cant bit of the first byte of the destination address field)
is 0, the frame is unicast, which indicates that the frame
is meant to be received by a single node. If the first bit
received is 1, the frame is multicast, which indicates
that the frame is meant to be received by a group of
nodes. If the destination address field contains all 1s,
the frame is broadcast, which is a special type of multi-
cast. Frames with the broadcast address in the destina-
tion address field are meant to be received by all nodes
on the local area network.
When a unicast frame arrives at the Am79C976 con-
troller, the controller will accept the frame if the destina-
tion address field of the incoming frame exactly
matches the 6-byte station address stored in the Phys-
ical Address registers (PADR, CSR12 to CSR14). The
byte ordering is such that the first byte received from
the network (after the SFD) must match the least signif-
icant byte of CSR12 (PADR[7:0]), and the sixth byte re-
ceived must match the most significant byte of CSR14
(PADR[47:40]).
When DRCVPA (CSR15, bit 13) is set to 1, the
Am79C976 controller will not accept unicast frames.
If the incoming frame is multicast, the Am79C976 con-
troller performs a calculation on the contents of the
destination address field to determine whether or not to
accept the frame. This calculation is explained in the
section that describes the Logical Address Filter
(LADRF).
When all bits of the LADRF registers are 0, no multicast
frames are accepted, except for broadcast frames.
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