AM79C976 Advanced Micro Devices, AM79C976 Datasheet - Page 154

• Manufacturer Part Number: AM79C976
• Description: PCnet-PRO 10/100 Mbps PCI Ethernet Controller
• Manufacturer: Advanced Micro Devices

154
11-9
3-1
Bit
16
15
14
13
12
8
7
6
5
4
0
TXSTRTINT
SPNDINT
TXDNINT
MREINT
MPINT
STINT
Name
UINT
RINT
SINT
TINT
RES
RES
RES
MII Management Read Error Interrupt. The MII Read Error interrupt is set by the Am79C976
controller to indicate that the currently read register from the external PHY is invalid. The contents
of the PHY Access Register are incorrect and that the operation should be performed again. The
indication of an incorrect read comes from the PHY. During the read turnaround time of the MII
management frame the external PHY should drive the MDIO pin to a LOW state. If this does not
happen, it indicates that the PHY and the Am79C976 controller have lost synchronization.
This bit is an alias of CSR7, bit 9
Reserved locations. Written as zeros and read as undefined.
Suspend Interrupt. This bit is set when a receiver or transmitter suspend operation has finished.
Magic Packet Interrupt. Magic Packet Interrupt is set by the Am79C976 controller when the device
is in the Magic Packet mode and the Am79C976 controller receives a Magic Packet frame.
This bit is an alias of CSR5, bit 4.
System Interrupt is set by the Am79C976 controller when it detects a system error during a bus
master transfer on the PCI bus. System errors are data parity error, master abort, or a target abort.
The setting of SINT due to data parity error is not dependent on the setting of PERREN (PCI
Command register, bit 6).
Note that because INEA is cleared by the STOP reset generated by the system error, the system
interrupt bypasses the global interrupt enable bits INEA and INTREN. This means that if SINTEN
in INTEN0 or SINTE in CSR5 is set to 1, INTA will be asserted when SINT is 1 regardless of the
state of INEA and INTREN.
The state of SINT is not affected by clearing any of the PCI Status register bits that get set when a
data parity error (DATAPERR, bit 8), master abort (RMABORT, bit 13), or target abort (RTABORT,
bit 12) occurs.
This bit is an alias of CSR5, bit 11.
Reserved locations. Written as zeros and read as undefined.
Transmit Interrupt is set by the Am79C976 controller after the OWN bit in the last descriptor of a
transmit frame has been cleared to indicate the frame has been copied to the transmit FIFO.
This bit is an alias of CSR0, bit 9.
User Interrupt. UINT is set by the Am79C976 controller after the host has issued a user interrupt
command by setting UINTCMD in the CMD0 register.
This bit is an alias of CSR4, bit 6.
Transmission Done Interrupt. This bit is set when the transmitter has finished sending a frame. This
bit is included for debugging purposes.
Transmit Start Interrupt. This bit is set when the transmitter begins the transmission of a frame. This
bit is included for debugging purposes.
This bit is an alias of CSR4, bit 3.
Software Timer Interrupt. The Software Timer interrupt is set by the Am79C976 controller when the
Software Timer counts down to 0. The Software Timer will immediately load the contents of the
Software Timer Value Register, STVAL, into the Software Timer and begin counting down.
This bit is an alias of CSR7, bit 11.
Reserved locations. Written as zeros and read as undefined.
Receive Interrupt is set by the Am79C976 controller after the last descriptor of a receive frame has
been updated by writing a 0 to the OWNership bit. RINT may also be set when the first descriptor
of a receive frame has been updated by writing a 0 to the OWNership bit if the LAPPEN bit in CMD2
has been set to a 1.
This bit is an alias of CSR0, bit 10.
P R E L I M I N A R Y
Am79C976
Description
8/01/00