AM79C976 Advanced Micro Devices, AM79C976 Datasheet - Page 57

• Manufacturer Part Number: AM79C976
• Description: PCnet-PRO 10/100 Mbps PCI Ethernet Controller
• Manufacturer: Advanced Micro Devices

Am79C976 logic will determine when a FIFO DMA
transfer is required. This transfer mode will be used for
transfers of data to and from the Am79C976 FIFOs.
Once the Am79C976 BIU has been granted bus mas-
tership, it will perform a series of consecutive transfer
cycles before relinquishing the bus. All transfers within
the master cycle will be either read or write cycles, and
all transfers will be transferred to contiguous, ascend-
ing addresses. Burst cycles are used whenever possi-
ble.
A burst transaction will start with an address phase, fol-
lowed by one or more data phases. AD[1:0] will always
be 0 during the address phase indicating a linear burst
order.
8/01/00
DEVSEL
FRAME
TRDY
C/BE
IRDY
REQ
GNT
PAR
CLK
AD
1
DEVSEL is sampled
P R E L I M I N A R Y
2
0110
MD2
3
Am79C976
PAR
4
0000
DATA
During FIFO DMA read operations, all byte lanes will
always be active. The Am79C976 controller will inter-
nally discard unused bytes. During the first and the last
data phases of a FIFO DMA burst write operation, one
or more of the byte enable signals may be inactive. All
other data phases will always write a complete DWord.
Figure 26 shows the beginning of a FIFO DMA write
with the beginning of the buffer not aligned to a DWord
boundary. The Am79C976 controller starts off by writ-
ing only three bytes during the first data phase. This op-
eration aligns the address for all other data transfers to
a 32-bit boundary so that the Am79C976 controller can
continue bursting full DWords.
5
PAR
6
0011
DATA
7
PAR
8
22929B27
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