AM79C976 Advanced Micro Devices, AM79C976 Datasheet - Page 230

• Manufacturer Part Number: AM79C976
• Description: PCnet-PRO 10/100 Mbps PCI Ethernet Controller
• Manufacturer: Advanced Micro Devices

230
Offset
0
4
4
4
4
4
4
4
4
4
4
31-0
Bit
31
30
29
28
27
26
25
24
23
22
RBADR[31:0]
FRAM
Name
OFLO
OWN
ERR
CRC
ENP
PAM
STP
Receive Buffer Address. This field contains the address of the receive buffer that is
associated with this descriptor.
This bit indicates whether the descriptor entry is owned by the host (OWN = 0) or by
the Am79C976 controller (OWN = 1). The host sets the OWN bit after it has emptied
the buffer pointed to by the descriptor entry. The Am79C976 controller clears the
OWN bit after filling the buffer that the descriptor points to. Both the Am79C976
controller and the host must not alter a descriptor entry after it has relinquished
ownership.
Error Summary. ERR is the OR of FRAM, OFLO, and CRC. ERR is set by the
Am79C976 controller and cleared by the host.
Framing error indicates that the incoming frame contains a non-integer multiple of
eight bits and there was an FCS error. If there was no FCS error on the incoming
frame, then FRAM will not be set even if there was a non-integer multiple of eight bits
in the frame. FRAM is not valid in internal loopback mode. FRAM is valid only when
ENP is set and OFLO is not. FRAM is set by the Am79C976 controller and cleared
by the host.
Overflow error indicates that the receiver has lost all or part of the incoming frame,
due to an inability to move data from the receive FIFO into a memory buffer before
the internal FIFO overflowed. OFLO is set by the Am79C976 controller and cleared
by the host.
CRC indicates that the receiver has detected a CRC (FCS) error on the incoming
frame. CRC is valid only when ENP is set and OFLO is not. CRC is set by the
Am79C976 controller and cleared by the host. CRC will also be set when Am79C976
controller receives an RX_ER indication from the external PHY through the MII.
Reserved.
Start of Packet indicates that this is the first buffer used by the Am79C976 controller
for this frame. If STP and ENP are both set to 1, the frame fits into a single buffer.
Otherwise, the frame is spread over more than one buffer. When LAPPEN (CSR3,
bit 5) is cleared to 0, STP is set by the Am79C976 controller and cleared by the host.
When LAPPEN is set to 1, STP must be set by the host.
End of Packet indicates that this is the last buffer used by the Am79C976 controller
for this frame. It is used for data chaining buffers. If both STP and ENP are set, the
frame fits into one buffer and there is no data chaining. ENP is set by the Am79C976
controller and cleared by the host.
Reserved.
Physical Address Match is set by the Am79C976 controller when it accepts the
received frame due to a match of the frame’s destination address with the content of
the physical address register. PAM is valid only when ENP is set. PAM is set by the
Am79C976 controller and cleared by the host.
This bit does not exist when the Am79C976 controller is programmed to use 16-bit
software structures for the descriptor ring entries (BCR20, bits 7-0, SWSTYLE is
cleared to 0).
P R E L I M I N A R Y
Am79C976
Description
8/01/00