AM79C976 Advanced Micro Devices, AM79C976 Datasheet - Page 180

• Manufacturer Part Number: AM79C976
• Description: PCnet-PRO 10/100 Mbps PCI Ethernet Controller
• Manufacturer: Advanced Micro Devices

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EXDINTE
MPPLBA
MPINT
MPINTE
effect. Read as undefined.
Broadcast Accept. If MPPLBA is
at its default value of 0, the
Am79C976 controller will only de-
tect a Magic Packet frame if the
destination address of the packet
matches the content of the physi-
cal address register (PADR). If
MPPLBA is set to 1, the destina-
tion address of the Magic Packet
frame can be unicast, multicast,
or broadcast. Note that the set-
ting of MPPLBA only affects the
address detection of the Magic
Packet frame. The Magic Packet
frame’s data sequence must be
made up of 16 consecutive phys-
ical addresses (PADR[47:0]) re-
gardless
destination address it has. This
bit is OR’ed with EMPPLBA bit
(CSR116, bit 6).
is set to 0 by H_RESET or
S_RESET and is not affected by
setting the STOP bit.
Packet Interrupt is set by the
Am79C976 controller when the
device is in the Magic Packet
mode and the Am79C976 con-
troller receives a Magic Packet
frame. When MPINT is set to 1,
INTA is asserted if IENA (CSR0,
bit 6) and the enable bit MPINTE
are set to 1.
Read/Write accessible. MPINT is
cleared by the host by writing a 1.
Writing a 0 has no affect. MPINT
is
S_RESET, or by setting the
STOP bit.
MPINTE is set to 1, the MPINT bit
will be able to set the INTR bit.
Read/Write accessible. MPINTE
is cleared to 0 by H_RESET or
S_RESET and is not affected by
setting the STOP bit.
Obsolete function. Writing has no
Magic Packet Physical Logical
Read/Write accessible. MPPLBA
Magic Packet Interrupt. Magic
Magic Packet Interrupt Enable. If
cleared
of
by
what
P R E L I M I N A R Y
H_RESET,
kind
Am79C976
of
2
1
0
MPEN
MPMODE
SPND
Read/Write accessible. MPEN is
cleared to 0 by H_RESET or
S_RESET and is not affected by
setting the STOP bit.
Read/Write
MODE is cleared to 0 by
H_RESET or S_RESET and is
not affected by setting the STOP
bit.
Requesting entrance into the
suspend mode by the host de-
pends on the setting of the
FASTSPNDE bit (CSR7, bit 15).
Refer to the bit description of the
FASTSPNDE bit and the Sus-
pend section in Detailed Func-
tions, Buffer Management Unit
for details.
In suspend mode, all of the CSR
and BCR registers are accessi-
ble. As long as the Am79C976
controller is not reset while in
suspend mode (by H_RESET,
S_RESET or by setting the STOP
bit), no re-initialization of the de-
vice is required after the device
lows activation of the Magic
Packet mode by the host. The
Am79C976 controller will enter
the Magic Packet mode when
both MPEN and MPMODE are
set to 1.
ter the Magic Packet mode when
MPMODE is set to 1 and either
PG is asserted or MPEN is set
to 1.
cause the Am79C976 controller
to start requesting entrance into
suspend mode. The host must
poll SPND until it reads back 1 to
determine that the Am79C976
controller has entered the sus-
pend mode. Setting SPND to 0
will get the Am79C976 controller
out of suspend mode. SPND can
only be set to 1 if STOP (CSR0,
bit 2) is set to 0. H_RESET,
S_RESET or setting the STOP bit
will get the Am79C976 controller
out of suspend mode.
Magic Packet Enable. MPEN al-
The Am79C976 controller will en-
Suspend. Setting SPND to 1 will
accessible.
8/01/00
MP-