AM79C976 Advanced Micro Devices, AM79C976 Datasheet - Page 219

• Manufacturer Part Number: AM79C976
• Description: PCnet-PRO 10/100 Mbps PCI Ethernet Controller
• Manufacturer: Advanced Micro Devices

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XPHYANE External PHY Auto-Negotiation
XPHYFD
XPHYSP
RES
external PHY. This bit is needed
when there is no way to guaran-
tee the state of the external PHY.
This bit must be reprogrammed
after every H_RESET.
Read/Write
YRST is set to 0 by H_RESET
and is unaffected by S_RESET
and the STOP bit. XPHYRST is
only valid when the internal Net-
work Port Manager is scanning
for a network port.
Enable. This bit will force the ex-
ternal PHY into enabling Auto-
Negotiation. When set to 0 the
Am79C976 controller will send a
MII management frame disabling
Auto-Negotiation.
Read/Write
XPHYANE
H_RESET and is unaffected by
S_RESET and the STOP bit.
XPHYANE is only valid when the
internal Network Port Manager is
scanning for a network port.
set, this bit will force the external
PHY into full duplex when Auto-
Negotiation is not enabled.
Read/Write accessible. XPHYFD
is set to 0 by H_RESET, and is
unaffected by S_RESET and the
STOP bit. XPHYFD is only valid
when the internal Network Port
Manager is scanning for a net-
work port.
this bit will force the external PHY
into 100 Mbps mode when Auto-
Negotiation is not enabled.
Read/Write accessible. XPHYSP
is set to 0 by H_RESET, and is
unaffected by S_RESET and the
STOP bit. XPHYSP is only valid
when the internal Network Port
Manager is scanning for a net-
work port.
ros and read as undefined.
External PHY Full Duplex. When
External PHY Speed. When set,
Reserved location. Written as ze-
is
accessible.
set
P R E L I M I N A R Y
accessible.
to
0
XPH-
Am79C976
by
1
0
Bit
31-16 RES
15-10 RES
9-5
4-0
MIIILP
RES
Name
PHYAD
REGAD
Read/Write accessible. MIIILP is
set to 0 by H_RESET and is unaf-
fected by S_RESET and the
STOP bit.
Read/Write accessible. PHYAD
is undefined after H_RESET and
is unaffected by S_RESET and
the STOP bit.
The PHYAD field is loaded from
bits [9:5] of the AUTOPOLL0 reg-
ister when AUTOPOLL0 is load-
ed from EEPROM.
ternal Loopback. When set, this
bit will cause the internal portion
of the MII data port to loop back
on itself. The interface is mapped
in
TXD[3:0] nibble data path is
looped back onto the RXD[3:0]
nibble data path. TX_CLK is
looped back as RX_CLK. TX_EN
is looped back as RX_DV. CRS is
correctly OR’d with TX_EN and
RX_DV and always encompass-
es the transmit frame. TX_ER is
looped back as RX_ER. Howev-
er, TX_ER will not get asserted
by the Am79C976 controller to
signal an error. The TX_ER func-
tion is reserved for future use.
ros and read as undefined.
zeros and read as undefined.
zeros and read as undefined.
dress. PHYAD contains the 5-bit
PHY Address field that is used in
the management frame that gets
clocked out via the MII manage-
ment port pins (MDC and MDIO)
whenever a read or write transac-
tion occurs to BCR34. The PHY
address 1Fh is not valid.
Address. REGAD contains the
Media Independent Interface In-
Reserved location. Written as ze-
Description
Reserved locations. Written as
Reserved locations. Written as
MII Management Frame PHY Ad-
MII Management Frame Register
the
following
way.
219
The