AM79C976 Advanced Micro Devices, AM79C976 Datasheet - Page 151

• Manufacturer Part Number: AM79C976
• Description: PCnet-PRO 10/100 Mbps PCI Ethernet Controller
• Manufacturer: Advanced Micro Devices

Offset 0C8h
8/01/00
FLOW: Flow Control Register
31-24
22-21
Bit
23
20
19
18
17
FCPEN
Name
VAL2
FIXP
RES
RES
NPA
FPA
Reserved locations. Written as zeros and read as undefined.
Value bit for byte 2. The value of this bit is written to any bits in the FLOW register that correspond
to bits in the FLOW[22:16] bit map field that are set to 1.
Reserved locations. Written as zeros and read as undefined.
Force Pause Ability. When this bit is set, Pause Ability is enabled regardless of the Pause Ability
state of the external PHY’s link partner. When Pause Ability is enabled, the receipt of a MAC
Control Pause Frame causes the device to stop transmitting for a time period that is determined by
the contents of the Pause Frame.
If a logical 1 is written to this bit position, the corresponding bit in the register will be loaded with
the contents of the VAL2 bit. If a logical 0 is written to this bit position, the corresponding bit in the
register will not be altered.
Negotiate Pause Ability. When this bit is set and the Force Pause Ability bit is not set, Pause Ability
is enabled only if the auto-negotiation process determines that the external PHY’s link partner
supports IEEE 802.3 flow control. When Pause Ability is enabled, the receipt of a MAC Control
Pause Frame causes the device to stop transmitting for a time period that is determined by the
contents of the Pause Frame.
If a logical 1 is written to this bit position, the corresponding bit in the register will be loaded with
the contents of the VAL2 bit. If a logical 0 is written to this bit position, the corresponding bit in the
register will not be altered.
Fixed Length Pause. When this bit is set to 1, all MAC Control Pause Frames transmitted from the
device will contain a Request_operand field that is copied from the PAUSE_LEN field of this
register.
When this bit is cleared to 0, a Pause Frame with its Request_operand field set to 0FFFFh will be
sent when the FCCMD bit in this register is changed from 0 to 1 or when the signal on the FC pin
changes from 0 to 1 while the FCPEN bit has the value 1. Also a Pause Frame with its
Request_operand field set to 0000h will be sent when the FCCMD bit in this register is changed
from 1 to 0 or when the signal on the FC pin changes from 1 to 0 while the FCPEN bit has the value
1.
If a logical 1 is written to this bit position, the corresponding bit in the register will be loaded with
the contents of the VAL2 bit. If a logical 0 is written to this bit position, the corresponding bit in the
register will not be altered.
Flow Control Pin Enable. When the value of this bit is 1, MAC Control Pause frames will be
transmitted or half-duplex back pressure will be applied when the FC pin is asserted. When the
value of this bit is 0, the state of the FC pin is ignored.
If a logical 1 is written to this bit position, the corresponding bit in the register will be loaded with
the contents of the VAL2 bit. If a logical 0 is written to this bit position, the corresponding bit in the
register will not be altered.
Table 57.
P R E L I M I N A R Y
FLOW: Flow Control Register
Am79C976
FLOW is a command-style register. All bits in this reg-
ister are cleared to 0 when the RST pin is asserted, be-
fore the serial EEPROM is read, and after a serial
EEPROM read error.
Description
151