AM79C976 Advanced Micro Devices, AM79C976 Datasheet - Page 134

• Manufacturer Part Number: AM79C976
• Description: PCnet-PRO 10/100 Mbps PCI Ethernet Controller
• Manufacturer: Advanced Micro Devices

134
Bit
6
5
4
3
2
1
0
APAD_XMT
CHDPOLL
TXDPOLL
EXLOOP
LAPPEN
INLOOP
Name
DRTY
Auto Pad Transmit. When set, APAD_XMT enables the automatic padding feature. Transmit frames
will be padded to extend them to 64 bytes including FCS. The FCS is calculated for the entire frame,
including pad, and appended after the pad field. When the auto padding logic modifies a frame, a
valid FCS field will be appended to the frame, regardless of the state of the DXMTFCS bit (CMD2,
bit 8) and of the ADD_FCS bit in the transmit descriptor.
This bit is an alias of CSR4, bit 11.
Disable Retry. When DRTY is set to 1, the Am79C976 controller will attempt only one transmission.
In this mode, the device will not protect the first 64 bytes of frame data in the Transmit FIFO from
being overwritten, because automatic retransmission will not be necessary. When DRTY is set to
0, the Am79C976 controller will attempt 16 transmissions before signaling a retry error.
This bit is an alias of CSR15, bit 5.
Internal Loopback. When this bit is set, the transmitter is internally connected to the receiver so that
the TXD[3:0] outputs are connected internally to the RXD[3:0] inputs, the TX_EN output is
connected to the RX_DV input, and RX_CLK is connected to TX_CLK. The device is forced into
full duplex mode so that collisions can not occur.
The INLOOP and EXLOOP bits should not be set at the same time.
Setting INLOOP to 1 is equivalent to setting LOOP (in CSR15) to 1 and MIIILP (in BCR32) to 1.
External Loopback. When this bit is set, the device is forced into full duplex mode so that collisions
can not occur during loop back testing. If the TXD[3:0] outputs are connected externally to the
RXD[3:0] inputs, the TX_EN output is externally connected to the RX_DV input, and RX_CLK is
connected to TX_CLK, then transmitted frames will also be received. This connection can be made
by attaching an external jumper or by programming an attached PHY to loopback mode.
The INLOOP and EXLOOP bits should not be set at the same time.
Setting EXLOOP to 1 is equivalent to setting LOOP (in CSR15) to 1 and MIIILP (in BCR32) to 0.
Look Ahead Packet Processing Enable. When set to a 1, the LAPPEN bit will cause the Am79C976
controller to generate an interrupt following the descriptor write operation to the first buffer of a
receive frame. This interrupt will be generated in addition to the interrupt that is generated following
the descriptor write operation to the last buffer of a receive packet. The interrupt will be signaled
through the RINT bit of CSR0 or the INT register.
Setting LAPPEN to a 1 also modifies the way the controller accesses the Receive Descriptors. See
the Look Ahead Packet Processing section.
This bit is an alias of CSR3, bit 5.
See Appendix A for more information on the Look Ahead Packet Processing concept.
Disable Chain Polling. If CHDPOLL is set, the Buffer Management Unit will disable chain polling.
Likewise, if CHDPOLL is cleared, automatic chain polling is enabled. If CHDPOLL is set and the
Buffer Management Unit is in the middle of a buffer-changing operation, setting the RDMD bit in
CMD0 or CSR7 will cause a poll of the current receive descriptor, and setting the TDMD bit in
CMD0 or CRR0 will cause a poll of the current transmit descriptor. If CHDPOLL is set, the RDMD
bit in CSR7 or CMD0 can be set to initiate a manual poll of a receive or transmit descriptor if the
Buffer Management Unit is in the middle of a buffer-chaining operation.
This bit is an alias of CSR7, bit 12.
Disable Transmit Polling. If TXDPOLL is set, the Buffer Management Unit will disable transmit
polling. Likewise, if TXDPOLL is cleared, automatic transmit polling is enabled. If TXDPOLL is set,
TDMD bit in CSR0 or CMD0 must be set in order to initiate a manual poll of a transmit descriptor.
Transmit descriptor polling will not take place if TXON is reset. Transmit polling will take place
following Receive activities.
This bit is an alias of CSR4, bit 12.
P R E L I M I N A R Y
Am79C976
Description
8/01/00