Z16F2800100ZCOG Zilog, Z16F2800100ZCOG Datasheet - Page 101

• Manufacturer Part Number: Z16F2800100ZCOG
• Description: DEV KIT FOR Z16F ZNEO
• Manufacturer: Zilog
• Series: ZNEO™r
• Type: MCUr

Specifications of Z16F2800100ZCOG

• Contents: Evaluation Board, Software and Documentation
• For Use With/related Products: Z16F Series
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4537

Table 43. Last IRQ Register (LASTIRQ)
PS022008-0810
BITS
FIELD
RESET
R/W
ADDR
Last IRQ Register
Interrupt Request 0 Register
Always 0
R
7
0
Reserved—These bits are reserved
WDTOSC—WDT Oscillator Fail
If this bit is 1, a WDT oscillator fail exception occurred. Writing 1 to this bit clears it to 0.
PRIOSC—Primary Oscillator Fail
If this bit is 1, a primary oscillator fail exception occurred. Writing 1 to this bit clears it
to 0.
WDT—Watchdog Timer Interrupt
If this bit is 1, a WDT exception occurred. Writing 1 to this bit clears it to 0.
When an interrupt occurs, the 5th bit value of the interrupt vector is stored in the register.
This register allows the software to determine which interrupt source was last serviced.
It is used by RTOS which have a single interrupt entry point. To implement this the
software must set all interrupt vectors to the entry point address. The entry point service
routine then reads this register to determine which source caused the interrupt or exception
and respond accordingly.
The interrupt request 0 (IRQ0) register (see
requests for both vectored and polled interrupts. When a request is presented to the
interrupt controller, the corresponding bit in the IRQ0 register becomes 1. If interrupts are
globally enabled (vectored interrupts), the interrupt controller passes an interrupt request
to the ZNEO CPU. If interrupts are globally disabled (polled interrupts), the ZNEO CPU
reads the interrupt request 0 register to determine if any interrupt requests are pending.
Writing 1 to the bits in this register clears the interrupt. The bits of this register are set by
writing 1 to the interrupt request 0 set regsiter (IRQ0SET) at address FF_E031H.
R/W
6
0
R/W
5
0
P R E L I M I N A R Y
IRQADR
R/W
4
0
FF_E023H
Table 44
R/W
3
0
on page 87) stores the interrupt
R/W
2
1
Product Specification
ZNEO
Interrupt Controller
R
1
0
Always 00
Z16F Series
R
0
0
86