Z16F2800100ZCOG Zilog, Z16F2800100ZCOG Datasheet - Page 370

• Manufacturer Part Number: Z16F2800100ZCOG
• Description: DEV KIT FOR Z16F ZNEO
• Manufacturer: Zilog
• Series: ZNEO™r
• Type: MCUr

Specifications of Z16F2800100ZCOG

• Contents: Evaluation Board, Software and Documentation
• For Use With/related Products: Z16F Series
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4537

Table 197. UART Timing with CTS
PS022008-0810
Parameter
T
T
T
(Output)
(Input)
(Output)
1
2
3
CTS
DE
TXD
UART Timing
Abbreviation
CTS Fall to DE Assertion Delay
DE Assertion to TXD Falling Edge (Start)
Delay
End of Stop Bit(s) to DE Deassertion Delay
Figure 79
Clear To Send input pin (CTS) is used for flow control. In this example, it is assumed that
the Driver Enable polarity has been configured to be Active Low and is represented here
by DE. The CTS to DE assertion delay (T1) assumes the UART Transmit Data register has
been loaded with data prior to CTS assertion.
T
1
and
Table 197
T
2
Figure 79. UART Timing with CTS
Start
provide timing information for UART pins for the case where the
P R E L I M I N A R Y
Bit 0
Bit 1
2 * XIN period
1 * XIN period
1 Bit period
Min
Delay (ns)
Bit 7
2 * XIN period +
1 Bit period
1 Bit period +
1 * XIN period
2 * XIN period
Parity
Product Specification
Electrical Characteristics
ZNEO
Max
Stop
Stop Bit(s)
End of
Z16F Series
T
3
354