Z16F2800100ZCOG Zilog, Z16F2800100ZCOG Datasheet - Page 195

• Manufacturer Part Number: Z16F2800100ZCOG
• Description: DEV KIT FOR Z16F ZNEO
• Manufacturer: Zilog
• Series: ZNEO™r
• Type: MCUr

Specifications of Z16F2800100ZCOG

• Contents: Evaluation Board, Software and Documentation
• For Use With/related Products: Z16F Series
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4537

Operation
PS022008-0810
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During transfer, data is sent and received simultaneously by both master and slave
devices. Separate signals are required to transmit data, receive data, and the serial clock.
When a transfer occurs, a multibit (typically 8-bit) character is shifted out one data pin and
a multi-bit character is simultaneously shifted in on a second data pin. An 8-bit shift
register in the master and an 8-bit shift register in the slave is connected as a circular
buffer. The ESPI shift register is buffered to support back-to-back character transfers in
high performance applications.
A transaction is initiated when the transmit data register is written in the master device.
The value from the data register is transferred into the shift register and the transaction
begins. After the transmit data is loaded into the shift register, the Transmit Data register
Empty (TDRE) status bit asserts, indicating that transmit data register is written with the
next value. At the end of each character transfer, the shift register value (receive data) is
loaded into the receive data register. At that point the Receive Data register Full (RDRF)
status bit asserts. When software or DMA reads the receive data from the receive data
register, the RDRF signal deasserts.
The master sources the SCK and SS signal during the transfer.
Internal data movement (either by software or DMA) to/from the ESPI block is controlled
by the transmit data register empty (TDRE) and receive data register full (RDRF) signals.
These signals are read only bits in the ESPI status register. When either the TDRE or
RDRF bits assert, an interrupt is sent to the interrupt controller if the data interrupt request
enable (DIRQE) bit is set. The TDRE and RDRF signals also generate transmit and
receive DMA requests.
such a case, either the TDRE or RDRF interrupts/DMA requests is disabled to minimize
software/DMA overhead. Unidirectional data transfer is supported by setting the
In many cases the software application is only moving information in one direction. In
Mode register:
– Added SSMD field which adds support for loop back and I2S modes.
– Moved SSV bit to the transmit data command register as described above.
– Added slave select polarity (SSPO) to support active High and Low slave select on
Status register:
– IRQ split into TDRE and RDRF (separate transmit and receive interrupts).
– Replace overrun error with separate transmit under-run and receive overrun.
State register.
– Replaced SCKEN bit with SCKI.
– Replaced TCKEN with SDI.
SS pin.
P R E L I M I N A R Y
Enhanced Serial Peripheral Interface
Product Specification
ZNEO
Z16F Series
179