Z16F2800100ZCOG Zilog, Z16F2800100ZCOG Datasheet - Page 224

• Manufacturer Part Number: Z16F2800100ZCOG
• Description: DEV KIT FOR Z16F ZNEO
• Manufacturer: Zilog
• Series: ZNEO™r
• Type: MCUr

Specifications of Z16F2800100ZCOG

• Contents: Evaluation Board, Software and Documentation
• For Use With/related Products: Z16F Series
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4537

PS022008-0810
Start and Stop Conditions
Arbitration Lost interrupts
Arbitration Lost interrupts (
in Master mode and loses arbitration (outputs a 1 on SDA and receives a 0 on SDA). The
I
when the I2CISTAT register is read.
Stop/Restart interrupts
A Stop/Restart event interrupt (
is in SLAVE mode and a Stop or Restart condition is received, indicating the end of the
transaction. The
a Stop or Restart condition. When a Restart occurs, a new transaction by the same Master
is expected to follow. This bit is cleared automatically when the I2CISTAT register is read.
The Stop/Restart interrupt only occurs on a selected (address match) slave.
Not Acknowledge interrupts
Not Acknowledge interrupts (
Not Acknowledge is received or sent by the I
not set in the
clears by setting the START or STOP bit. When this interrupt occurs in Master mode, the
I
Not Acknowledge interrupt occurs when a Not Acknowledge is received in response to the
data sent. The
General Purpose Timer Interrupt from Baud Rate Generator
If the I
the I2CCTL register = 1, an interrupt is generated when the BRG counts down to 1. The
BRG reloads and continues counting, providing a periodic interrupt. None of the bits in
the I2CISTAT register are set, allowing the BRG in the I
general purpose timer when the I
The Master generates the Start and Stop conditions to start or end a transaction. To start a
transaction, the I
while SCL is High. To complete a transaction, the I
condition by creating a Low-to-High transition of the SDA signal while the SCL signal is
High. The START and STOP events occur when the START and STOP bits in the I
Control register are written by software to begin or end a transaction. Any byte transfer
currently under way finishes, including the acknowledge phase before the START or
STOP condition occurs.
2
2
C Controller switches to SLAVE mode when this occurs. This bit clears automatically
C Controller waits until it is cleared before performing any action. In SLAVE mode, the
2
C Controller is disabled (
I
2
NCKI
C Control
RSTR
2
C Controller generates a Start condition by pulling the SDA signal Low
bit clears in Slave mode when software reads the I2CISTAT register.
bit in the
Register. In MASTER mode the Not Acknowledge interrupt
P R E L I M I N A R Y
ARBLST
NCKI
SPRS
I
2
2
IEN
C State Register
C Controller is disabled.
bit = 1 in I2CISTAT) occur in Master mode when a
bit = 1 in I2CISTAT) occur when the I
bit = 1 in I2CISTAT) occurs when the I
bit in the I2CCTL register = 0) and the
2
C Controller and the START or STOP bit is
indicates whether the bit was set due to
2
C Controller generates a STOP
2
C Controller to be used as a
I
2
C Master/Slave Controller
Product Specification
ZNEO
2
C Controller is
2
Z16F Series
C Controller
BIRQ
bit in
2
C
208