Z16F2800100ZCOG Zilog, Z16F2800100ZCOG Datasheet - Page 238

• Manufacturer Part Number: Z16F2800100ZCOG
• Description: DEV KIT FOR Z16F ZNEO
• Manufacturer: Zilog
• Series: ZNEO™r
• Type: MCUr

Specifications of Z16F2800100ZCOG

• Contents: Evaluation Board, Software and Documentation
• For Use With/related Products: Z16F Series
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4537

PS022008-0810
S
Slave Address
1st Byte
Figure 50. Data Transfer Format - Slave Transmit Transaction with 10-Bit Address
12. Software responds to the STOP/RESTART interrupt by reading the I2CISTAT register
Slave Transmit (Master Read) Transaction with 10-Bit Address
Figure 50
bit addressing.
The following procedure describes the I
10-bit addressing mode, transmitting data to the bus Master:
1. Software configures the controller for operation as a Slave in 10-bit addressing mode.
2. The Master initiates a transfer, sending the first address byte. 
3. The Master sends the second address byte. The Slave mode I
4. Software responds to the Slave Address Match interrupt by reading the I2CISTAT
5. The Master notifies the Acknowledge and sends a Restart instruction, followed by the
– Initialize the MODE field in the I
– Optionally set the
– Initialize the
– Set
– Program the Baud Rate High and Low Byte registers for the I
which clears the
The Slave mode I
SLA
acknowledges, indicating that it is available to accept the transaction.
the second address byte with the value in
the I2CISTAT register is set = 1, causing a Slave Address Match interrupt. The
is set = 0, indicating a write to the Slave. If a match occurs, the I
acknowledges on the I
register which clears the
first address byte with the R/W = 1. The Slave mode I
Restart followed by the first address byte with a match to
R/W = 1 (Master reads from Slave). The Slave I
W=0 A Slave Address
Master/Slave mode with 10-bit addressing.
I2CMODE register.
[9:8] and detects the R/W bit = 0 (write from Master to Slave). The I
displays the data transfer format for a Master reading data from a Slave with 10-
IEN
= 1,
2nd Byte
NAK
SLA
SPRS
2
C Controller recognizes the start of a 10-bit address with a match to
[7:0] bits in the I2CSLVAD register and
= 0 in the I
GCE
2
P R E L I M I N A R Y
bit.
C bus, indicating that it is available to accept the data.
SAM
bit.
A S Slave Address
bit. When the
2
C Control register.
2
2
C Master/Slave Controller operating as a Slave in
C Mode register for either Slave-only mode or
1st Byte
SLA
RD
[7:0]. If there is a match, the
bit = 0, no further action is required.
2
C Controller sets the
R=1
2
C Controller recognizes the
A
SLA
I
2
SLA
C Master/Slave Controller
Product Specification
2
Data
C Controller compares
[9:8] and detects the
ZNEO
2
[9:8] in the
2
C baud rate.
C Controller
A
SAM
2
Z16F Series
Data
C Controller
SAM
bit in the
RD
bit in
A P
bit
222