Z16F2800100ZCOG Zilog, Z16F2800100ZCOG Datasheet - Page 199

• Manufacturer Part Number: Z16F2800100ZCOG
• Description: DEV KIT FOR Z16F ZNEO
• Manufacturer: Zilog
• Series: ZNEO™r
• Type: MCUr

Specifications of Z16F2800100ZCOG

• Contents: Evaluation Board, Software and Documentation
• For Use With/related Products: Z16F Series
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4537

®
ZNEO
Z16F Series
Product Specification
183
software, is to set the
bit of the transmit data command register when the last TDRE
TEOF
interrupt or DMA request is being serviced (set TEOF before or simultaneously with
writing the last data byte). When the last bit of the last character is transmitted, the
hardware will automatically deassert the SSV and TEOF bits. The second method is for
software to directly clear the SSV bit after the transaction completes. If software clears the
SSV bit directly, it is not necessary for software to also set the TEOF bit on the last
transmit byte. After writing the last transmit byte, the end of the transaction is detected by
waiting for the last RDRF interrupt or monitoring the TFST bit in the ESPI Status register.
The transmit underrun and receive overrun errors do not occur in an SPI mode master. If
the RDRF and TDRE requests have not been serviced before the current byte transfer
completes, SCLK is paused until the data register is read and written. The transmit
underrun and receive overrun errors will occur in a slave if the slave’s software/DMA does
not keep up with the master data rate. If a transmit underrun occurs in SLAVE mode, the
shift register in the slave is loaded with all 1s.
In the SPI mode, the SCK is active only for the data transfer with one SCK period per bit
transferred. If the SPI bus has multiple slaves, the slave select lines to all or one of the
slaves must be controlled independently by software using GPIO pins.
Figure 37
on page 184 displays multiple character transfer in SPI mode. Note that while
character ’n’ is being transferred using the shift register, software/DMA responds to the
receive request for character n-1 and the transmit request for character n+1.
PS022008-0810
P R E L I M I N A R Y
Enhanced Serial Peripheral Interface