Z16F2800100ZCOG Zilog, Z16F2800100ZCOG Datasheet - Page 236

• Manufacturer Part Number: Z16F2800100ZCOG
• Description: DEV KIT FOR Z16F ZNEO
• Manufacturer: Zilog
• Series: ZNEO™r
• Type: MCUr

Specifications of Z16F2800100ZCOG

• Contents: Evaluation Board, Software and Documentation
• For Use With/related Products: Z16F Series
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4537

PS022008-0810
Figure 49. Data Transfer Format - Slave Transmit Transaction with 7-bit Address
2. The Master initiates a transfer by sending the first address byte. The I
3. The Master sends the second address byte. The Slave mode I
4. Software responds to the interrupt by reading the I2CISTAT register, which clears the
5. The Master detects the Acknowledge and sends the first byte of data.
6. The I
7. Software responds by reading the I2CISTAT register, finding the
8. The Master and Slave loops on steps 5–7 until the Master detects a Not Acknowledge
9. The Master sends the STOP or RESTART signal on the bus. Either of these signals
Slave Transmit Transaction with 7-bit Address
The data transfer format for a Master reading data from a Slave in 7-bit address mode is
shown in
operating as a Slave in 7-bit addressing mode, transmitting data to the bus Master.
S
recognizes the start of a 10-bit address with a match to
bit = 0 (write from Master to Slave). The I
it is available to accept the transaction.
address match between the second address byte and
I2CISTAT register is set = 1, causing an interrupt. The
write to the Slave. The I
accept the data.
SAM
data is received. If software is only able to accept a single byte it sets the
I2CCTL register.
Acknowledge, depending on the state of the
controller generates the receive data interrupt by setting the
register.
then reading the I2CDATA register, which clears the
only one more data byte, it sets the
instruction or runs out of data to send.
cause the I
register). When the Slave receive data from the Master, software takes no action in
response to the Stop interrupt other than reading the I2CISTAT register, clearing the
STOP bit.
bit. When
2
Figure
C controller receives the first byte and responds with Acknowledge or Not
2
C Controller to assert the Stop interrupt (STOP bit = 1 in the I2CISTAT
Address
49. The following procedure describes the I
Slave
RD
= 0, no immediate action is taken by software until the first byte of
P R E L I M I N A R Y
2
C Controller Acknowledges, indicating it is available to
R=1
NAK
A
bit in the I2CCTL register.
2
C Controller acknowledges, indicating that
NAK
Data
bit in the I2CCTL register. The I
SLA
RDRF
RD
SLA
A
[7:0]. The
2
C Master/Slave Controller
bit is set = 0, indicating a
I
2
bit. If software accepts
[9:8] and detects the R/W
RDRF
C Master/Slave Controller
Product Specification
2
C Controller detects an
ZNEO
Data
RDRF
bit in the I2CISTAT
SAM
2
C Controller
bit = 1 and
bit in the
Z16F Series
NAK
A
bit in the
P/S
2
C
220